You need to specify what CPU you are talking about.
The M6809 uses such syntax to indicate register indirect or indexed addressing with no offset. It is the same as 0,R where R is any of X, Y, U, S. There is also ,R+ ,R++ ,-R and ,--R
If the assembler is smart it should generate ,R if you write 0,R. They both use the same amount of code, but no offset at all takes 1 cycle less than a 5 bit offset.