Electronics > Microcontrollers

Open-source software for Verilog synthesis

(1/6) > >>

Unixon:
Recently I was looking for an open-source toolchain to synthesize a low-level ASIC description (i.e. gate level or even switch level) from a Verilog source.

A part of software was found at http://opencircuitdesign.com/ site, other tools are notably the VTR (Verilog-to-Routing) http://code.google.com/p/vtr-verilog-to-routing/ and currently a part of it, the Odin-II project http://code.google.com/p/odin-ii/, the GNU Electric http://www.gnu.org/software/electric/ for the lowest silicon cell level, also the Yosis package http://www.clifford.at/yosys/ for high level synthesis.

As far as I understand, altogether these tools should allow for complete ASIC development cycle.
Well, using Odin-II I've managed to get to a netlist stage with respect to some generic FPGA and then a lot of questions came up.

Does anybody have any experience with mentioned software?

clifford:
Yes. I'm actually the Author of Yosys.

The Yosys manual [1] contains an Appendix (atm it's App. E) titled "Evaluation of other OSS Verilog Synthesis Tools". I evaluated the synthesis feature of Icarus Verilog, VTR / Odin-II, HANA and VIS. I was not pleased. So I wrote my own tool.

If you are interested in ASIC synthesis, Yosys will get you from Verilog to a gate level netlist. From there you can use tools like ABC [2] for gate-level optimization and technology mapping.

Atm I'm working on extending the Yosys features for FPGA synthesis (including mapping of high-level cells like DSP cells and block RAM). I also have a half-finished projects in which I'm using Yosys to reverse-engineer a sequential logic  netlist from the MOS6052 transistor netlists provided by the Visual6502 project.

The aim on Yosys is to provide a framework for all kinds of logic synthesis and analysis work, by providing a (ever growing) set of basic algorithms and an entry point to utilize lower-level tools such as ABC.

[1] http://www.clifford.at/yosys/files/manual.pdf
[2] http://www.eecs.berkeley.edu/~alanmi/abc/

Unixon:
Great! :)

I have some ideas for ASICs, but, prior to digging into depths of Verilog implementations of various circuits and running them on FPGAs, I want to step aside of this mainline and do few [weird] things about synthesis.

1) Learn how to synthesize an ASIC all the way down to GDS cells to understand this design flow well; Maybe, play around a bit with low-level simulations.
2) Synthesize Verilog source into discrete elements / standard CMOS ICs as elementary cells, this should be similar to inventing a custom FPGA architecture;
It should be possible to load the output of this stage into EDA tool like Eagle or KiCAD and then turn it into a real device on a PCB. There's not much practical sense in really doing a hardware like this, but this might be a great way for people learning stuff. I find fascinating the very idea that one can make a non-FPGA prototype of an ASIC with just the same approach and tools as a real chip.
3) Take the design flow developed in (1) and (2) and go back to implementing ideas, equipped with tools for producing a virtual IC or even a real prototype (not FPGA based);

Currently I'm stuck at the stage of producing gate-level description without complex blocks like adders, multiplexers, LUTs etc., just with bare gates.

clifford:
Let me address your last point first: Producing a gate-level netlist using yosys is really simple. A step-by-step howto for exactly this basic application is included in the README file:

https://github.com/cliffordwolf/yosys/blob/master/README

The paper [1] I wrote for the Austrochip conference contains examples for gate-level synthesis, fpga synthesis (luts) and coarse-grain synthesis (adders, etc.). I will put it online on the yosys website after the conference (mid. october).

Regarding 2) and 3): There is a lot in yosys that can help you there. Yosys is design with so-called coarse-grain synthesis in mind. (Coarse-grain synthesis is synthesis for architectures with coarse-grain cells like addders or even more complex cells such as ALUs.) I co-authored a book chapter [2] on using yosys not only for synthesis for coarse grain architectures but also using yosys in designing such architectures by analyzing example designs. It is to appear in fall and I will also put a copy of this book chapter on the website when it comes out.

Regarding 1): Yosys purely operates on a netlist level and does not do physical layout. I think this is good, because layout synthesis requires a fairly different set of algorithms and data structures and therefore is best done in a separate tool. There are some open source tools that can do layout (gnu electric, alliance), but I have no experience whatsoever with this tools and do not know if they can do layout synthesis and if so if they are any good at it.

[1] Clifford Wolf, Johann Glaser. Yosys - A Free Verilog Synthesis Suite. Austrochip 2013. to appear.

[2] Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. In Jan Haase, editor, Advances in Models, Methods, and Tools for Complex Chip Design — Selected contributions from FDL’12. Springer, 2013. to appear.

Unixon:

--- Quote from: clifford on September 13, 2013, 10:00:19 pm ---Let me address your last point first: Producing a gate-level netlist using yosys is really simple. A step-by-step howto for exactly this basic application is included in the README file: https://github.com/cliffordwolf/yosys/blob/master/README

--- End quote ---

Yes, this is exactly what I tried first. After "write_verilog synth.v" I end up with another verilog source, writing ilang doesn't really help either and I still didn't see anything in intersynth format, that thing seem to dislike trivial verilog examples. Flattening a design looks promising, only D flip-flops are left out of complex components. But how do I convert this to any usable form? Odin-II at least gave me BLIF file which I was able to convert further into SPICE netlist with some success.  I can't figure out what should I do with Yosys output.

Navigation

[0] Message Index

[#] Next page