1.) The container is not an issue. You could simple write a S-expression to XML converter and convert EDIF to XML. The question is how you organize the data _within_ the container. For an "as easy to process as possible" format I would expect something line-based with whitespace separated tokens or maybe JSON.
I don't insist on inventing a new format, indeed, I think it would be better if it is something already being used in practice.
My suggestion of XML was due to good impression of working with Eagle CAD XML-based format. This is not about ASICs at all, I just liked the approach.
2.) It must provide a unique advantage. I understood (but maybe I understood wrong) that you wanted something that is easy to parse and process and that you therefore are unhappy with the existing options (Verilog Netlists, ILANG, EDIF and now SPICE).
OK, let's look at what is already there.
1) Verilog Netlists : it's still a valid Verilog source may contain any of valid Verilog language elements, not very trivial syntax, no cell definitions; Maybe this is OK, but I need to see how it looks for more complex input.
2) ILANG : clear syntax, contains additional information for entities; Same as above, but I like this more for regular structure.
3) EDIF : complex syntax, language-specific elements; I don't have a library like TinyXML to deal with LISP structures.
4) SPICE : easy syntax, but it doesn't contain cell descriptions, has implicit assignments of wires to cells' ports; Simple, good, but lacks some info.
I think ILANG wins here, maybe I should work directly with RTLIL by writing a backend for Yosys.