As said above, it isn't solvable in the general case.

Now depending on the characteristics of the input PWM signal (is the frequency arbitrary, but fixed over a large number of PWM cycles, is there a defined min an max frequency you can rely on, for instance) and your expectations, you may be able to work something out.

I'm thinking of something as the following: if it's acceptable not to be cycle-accurate, you could implement a PWM frequency and duty cycle estimator based on a few input PWM cycles in a moving average manner, and set your output signal with those parameters (limiting the duty cycle would then just be a matter of limiting the estimated input duty cycle). Of course it would degrade the frequency response, delay and resolution, but it may be acceptable depending on your requirements. To handle the 100% duty cycle case, you could have a state machine that would use a default output frequency until your frequency estimator settles (that is, until it has seen a few PWM cycles with transitions to low level, thus a duty cycle < 100%, allowing it to determine both the period and duty cycle). The other case, considering your frequency estimator has settled and then there are pulses with 100% duty cyle (that you would detect if the input signal is high for longer than the max PWM period you defined (min frequency), would either reset your state machine (thus resetting the frequency estimator to a default value), or the frequency estimator would use the last estimated frequency until it can estimate a new one.

Obviously as said above that has limitations so you'd have to determine whether those are acceptable.