PIC MCU for audio format conversion task (I2S)

[Toney]

I want to perform the following audio conversion, where the top three rows are the desired I2S output, and the bottom four rows are the inputs (clock, separate inputs for left/right channels and a word clock for which only the falling edge is known). The latency can be higher than in the picture below and I have an external clocking resource to get both of the clocks as an input. The slower clock runs at ~4 mhz, and the faster clock at ~6 mhz.



For a PIC14 development board, is there some MCU that can complete the conversion task?

The problem I had is that the faster clock runs at 6 mhz, affording only a few instructions per clock cycle on even the fastest MCUs. But perhaps there is some MCU that can stream and send all the bits of one block at once, thus making the conversion possible.

[SiliconWizard]

Not completely sure I get the exact format of your inputs from your description and small capture. Could that feed a standard SPI peripheral? If so, I guess some MCU with two SPI peripherals and one I2S could do.

Otherwise, don't expect to be able to "bit-bang" that on a MCU, especially a small one.
One "obvious" solution would be to use a CPLD/small FPGA to do this (if, again, your inputs can't be decoded with a standard SPI peripheral/or otherwise serial engine that can accomodate them.)

[Toney]

The input data format is the following, on falling edge of the base clock (88200 * 32 hz) both the L and R outputs are sent. The outputs are 18-bit words in a 32-bit block, start of which is given by the falling edge of the word clock.

And the output is standard 24-bit 88.2 khz I2S with two channels.

I think it could feed an SPI peripheral, however it is three data lines so I am not sure if such MCU exists for the 14-pin board.

Yes, the picture is from ISE simulation. I would like to use an MCU since I already have a board + programmer, and it seems the CLPDs are being phased out by Xilinx.

[SiliconWizard]

The input data format is the following, on falling edge of the base clock (88200 * 32 hz) both the L and R outputs are sent. The outputs are 18-bit words in a 32-bit block, start of which is given by the falling edge of the word clock.

And the output is standard 24-bit 88.2 khz I2S with two channels.

I think it could feed an SPI peripheral, however it is three data lines so I am not sure if such MCU exists for the 14-pin board.

From your description above, it looks like you could use SPI indeed. Since you have 2 data lines, that's why I mentioned 2 SPI peripherals. Any MCU with 2 SPI peripherals could be used; just feed the same clock and "word" signal to both, and each its own data line. Done. You'll get each channel on a separate SPI. Not a problem at all. Some MCUs also have "QSPI" peripherals, supporting up to 4  data lines, so that could be used too.

I'm not sure what exactly you are looking for in terms of MCU and what you mean by this "14-pin board". MCUs with 2 SPI and 1 I2S, or 1 QSPI and 1 I2S are many, but not sure at all you'll find them if you restrict yourself to one specific board supporting only a very limited set of very small PIC MCUs. If that's what you're after, I'd really suggest looking elsewhere.

Yes, the picture is from ISE simulation. I would like to use an MCU since I already have a board + programmer, and it seems the CLPDs are being phased out by Xilinx.

I highly doubt that. But these days, there are many small FPGAs out there that are almost as cheap as MCUs and more than capable enough for this. You can take a look at Lattice's offering for instance. MachXO2/MachXO3/iCE40... You can find dev boards starting at $20-$25 or so... and iCE40 FPGAs start at just a couple bucks per one too.

[Toney]

The input data format is the following, on falling edge of the base clock (88200 * 32 hz) both the L and R outputs are sent. The outputs are 18-bit words in a 32-bit block, start of which is given by the falling edge of the word clock.

And the output is standard 24-bit 88.2 khz I2S with two channels.

I think it could feed an SPI peripheral, however it is three data lines so I am not sure if such MCU exists for the 14-pin board.

From your description above, it looks like you could use SPI indeed. Since you have 2 data lines, that's why I mentioned 2 SPI peripherals. Any MCU with 2 SPI peripherals could be used; just feed the same clock and "word" signal to both, and each its own data line. Done. You'll get each channel on a separate SPI. Not a problem at all. Some MCUs also have "QSPI" peripherals, supporting up to 4  data lines, so that could be used too.

I'm not sure what exactly you are looking for in terms of MCU and what you mean by this "14-pin board". MCUs with 2 SPI and 1 I2S, or 1 QSPI and 1 I2S are many, but not sure at all you'll find them if you restrict yourself to one specific board supporting only a very limited set of very small PIC MCUs. If that's what you're after, I'd really suggest looking elsewhere.

Yes, the picture is from ISE simulation. I would like to use an MCU since I already have a board + programmer, and it seems the CLPDs are being phased out by Xilinx.

I highly doubt that. But these days, there are many small FPGAs out there that are almost as cheap as MCUs and more than capable enough for this. You can take a look at Lattice's offering for instance. MachXO2/MachXO3/iCE40... You can find dev boards starting at $20-$25 or so... and iCE40 FPGAs start at just a couple bucks per one too.

I meant a developer board for the 14-pin MCUs, unfortunately no MCU with the feature set according to the microchip explorer.

So I suppose CLPD/FPGA makes sense. This is DIY, I am only making two chips, so the adapter/dev board price is more important. What kind of adapter does Lattice require? I suppose a Xilinx CLPD (either CoolRunner or XC9572XL) is also fine, the cable is $20 from China, the development board around the same. One problem is that I can't seem to only purchase two of the chips.

[SiliconWizard]

Lattice's "breakout boards" are self-sufficient. They contain an IC to allow programming from USB without any external tool.

[Toney]

Lattice's "breakout boards" are self-sufficient. They contain an IC to allow programming from USB without any external tool.

Excellent. 

Which design would you recommend (I looked at the iCE Ultralite and LP series)? Are there surface mount adapters for some of the packages available as with the smaller Xilinx designs? Going with the FPGA route I should convert direct to SPIDF and multiply the clock on board so the design with PLL is better, although with the 50 mhz clock the jitter is still probably going to be in +/- 20ns (1/4 cycle) as required by the standard. The peak to peak output of SPIDF is quite narrow at 0.4-0.6 V, is the FPGA consistent enough?

[SiliconWizard]

Lattice's "breakout boards" are self-sufficient. They contain an IC to allow programming from USB without any external tool.

Excellent. 

Which design would you recommend (I looked at the iCE Ultralite and LP series)? Are there surface mount adapters for some of the packages available as with the smaller Xilinx designs? Going with the FPGA route I should convert direct to SPIDF and multiply the clock on board so the design with PLL is better, although with the 50 mhz clock the jitter is still probably going to be in +/- 20ns (1/4 cycle) as required by the standard. The peak to peak output of SPIDF is quite narrow at 0.4-0.6 V, is the FPGA consistent enough?

Is that a one-off project or are you going to build it in quantities?

[Toney]

Lattice's "breakout boards" are self-sufficient. They contain an IC to allow programming from USB without any external tool.

Excellent. 

Which design would you recommend (I looked at the iCE Ultralite and LP series)? Are there surface mount adapters for some of the packages available as with the smaller Xilinx designs? Going with the FPGA route I should convert direct to SPIDF and multiply the clock on board so the design with PLL is better, although with the 50 mhz clock the jitter is still probably going to be in +/- 20ns (1/4 cycle) as required by the standard. The peak to peak output of SPIDF is quite narrow at 0.4-0.6 V, is the FPGA consistent enough?

Is that a one-off project or are you going to build it in quantities?

It is a one-off project, possibly on veroboard. I plan to make two in total.

[SiliconWizard]

Then I wouldn't bother with the packages and adapters. Why not just use the breakout boards as is? Those Lattice ones are relatively small. A little less than 80mmx80mm.
As to the FPGA to choose - iCE40 are fine for this. MachXO2/XO3 would be fine too. Beware of MachXO3 though - some models have integrated Flash, others not, and I don't remember what the breakout boards include. MachXO2 are easy to use, available in QFP (if you ever want to make your own board later on), and have integrated Flash, so they don't need an external Flash chip.

As for the clock, integrated PLL's are probably more than adequate in terms of jitter - unless you were maybe thinking of building a very high-end HiFi thing. Integrated oscillators, OTOH, wouldn't be IMHO. They are just RC oscillators.

But if you are concerned, just use an external oscillator with the exact frequency you need - or a multiple, so that you can use an integrated clock divider rather than a PLL, which should give you less jitter.

[Toney]

Then I wouldn't bother with the packages and adapters. Why not just use the breakout boards as is? Those Lattice ones are relatively small. A little less than 80mmx80mm.
As to the FPGA to choose - iCE40 are fine for this. MachXO2/XO3 would be fine too. Beware of MachXO3 though - some models have integrated Flash, others not, and I don't remember what the breakout boards include. MachXO2 are easy to use, available in QFP (if you ever want to make your own board later on), and have integrated Flash, so they don't need an external Flash chip.

As for the clock, integrated PLL's are probably more than adequate in terms of jitter - unless you were maybe thinking of building a very high-end HiFi thing. Integrated oscillators, OTOH, wouldn't be IMHO. They are just RC oscillators.

But if you are concerned, just use an external oscillator with the exact frequency you need - or a multiple, so that you can use an integrated clock divider rather than a PLL, which should give you less jitter.

Yes, this sounds like a good idea.

With the clock I was talking about mostly the 10 pin boards which do not include PLL (it's in the datasheet), thus requiring oscillator for clock rate multiplication. The stream is not converted to analog as such so jitter is only a problem to the extent that the receiver won't accept the stream, no Hi-Fi.

I looked at the breakout boards, and the MachXO3D board is the cheap one and looks great too. Flash as in flash memory? Do I need this? The memory requirement should be no more than 200 bits. Searching through the data-sheet just now...

http://www.latticesemi.com/products/developmentboardsandkits/machxo3d_breakout_board
http://www.latticesemi.com/view_document?document_id=52590

[SiliconWizard]

I looked at the breakout boards, and the MachXO3D board is the cheap one and looks great too. Flash as in flash memory? Do I need this? The memory requirement should be no more than 200 bits.

I'm talking about the flash memory needed to configure the FPGA, not flash possibly used as user memory. Every FPGA needs this. Some FPGAs (such as those small Lattice ones) have embedded Flash for this, others do not.

The MachXO2 line has embedded flash for configuration in all models. The MachXO3 is different. Some models have embedded Flash, some do not, and either require an external Flash memory chip or just have an internal NVM that is not true flash and can only be reprogrammed a couple times. I remember some earlier breakout boards for the MachXO3 (I actually have one of these) had a model without embedded Flash, and I'm not sure they had external Flash either, so you could either program them a couple times for non-volatile use, or configure them every time you powered them on, doable for development but not exactly practical either.

The MachXO3D line is relatively new, and only has 2 models so far. Both have embedded configuration flash, so nothing to worry about here. They should be perfectly fine for your needs. The breakout board hosts the bigger one. Probably a bit overkill even for your needs, but the boards are cheap, so that's fine. Once you have tested them, you may actually find a lot more applications for those!

[Toney]

I looked at the breakout boards, and the MachXO3D board is the cheap one and looks great too. Flash as in flash memory? Do I need this? The memory requirement should be no more than 200 bits.

I'm talking about the flash memory needed to configure the FPGA, not flash possibly used as user memory. Every FPGA needs this. Some FPGAs (such as those small Lattice ones) have embedded Flash for this, others do not.

The MachXO2 line has embedded flash for configuration in all models. The MachXO3 is different. Some models have embedded Flash, some do not, and either require an external Flash memory chip or just have an internal NVM that is not true flash and can only be reprogrammed a couple times. I remember some earlier breakout boards for the MachXO3 (I actually have one of these) had a model without embedded Flash, and I'm not sure they had external Flash either, so you could either program them a couple times for non-volatile use, or configure them every time you powered them on, doable for development but not exactly practical either.

The MachXO3D line is relatively new, and only has 2 models so far. Both have embedded configuration flash, so nothing to worry about here. They should be perfectly fine for your needs. The breakout board hosts the bigger one. Probably a bit overkill even for your needs, but the boards are cheap, so that's fine. Once you have tested them, you may actually find a lot more applications for those!

Thanks, super informative! Ordering the chips now...