PIC micro controller counter

[khatus]

The maximum clock frequency at the T0CKI input is limited by the synchronization requirement with the internal clock. Each machine cycle (or instruction cycle) for a PIC microcontroller consists of four clock cycles, which are named as Q1, Q2, Q3, and Q4. The synchronization of T0CKI with the internal clock is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of each machine cycle. Therefore, the external clock signal at T0CKI should remain high or low for at least half of the duration of the machine cycle (which is 2Tosc, Tosc is the period for the main oscillator), plus an additional resistor-capacitor delay of 20 ns. This determines the minimum value of the pulse width that enters through the T0CKI pin. The minimum time period of the input clock pulse is, therefore, 4Tosc + 40 ns, and the maximum frequency will be the reciprocal of this.

I can't understand the line "The synchronization of T0CKI with the internal clock is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of each machine cycle".
Can anybody explain??

[Ian.M]

If you need to know what  Q2 and Q4 refer to, search the datasheet for the subsection "Instruction Flow/Pipelining"

[KL27x]

For example, say oscillator frequency is X Hz. Tosc is X^-1 seconds.
The TOCK1 input is sampled every other clock cycle.
If your signal has pulse widths that are narrower than 2 clock cycles, they can be missed. Anything shorter than 2Tosc or 2*X^-1 seconds
If your signal has frequency greater than (X/4) Hz, it cannot be accurately counted. If it is lower, it might be counted accurately; it might not.

A signal must be slower than  (X/4) Hz, and the the pulse widths (both hi and lo) must be greater than or equal to 2 clock cycles. So you could count a 50% duty cycle square wave at frequency approaching X/4 Hz. But if it were a 25% duty cycle square wave, you would be hitting the limit around X/8 Hz.

If the pulse width of your input is fixed and it is longer than 2(X Hz)^-1, you will start dropping pulses when the frequency is high enough to make the off half of the period get down to 2(X Hz)^-1.

(X/4) Hz is also the frequency of instruction execution. Many or most of the assembly instructions of an 8 bit PIC take 4Tosc to complete. Some take 8. It is (probably) irrelevant to you on which of these 4 ticks in the cycle the signal is sampled on. It's every other, and that's all that is important. Unless you have your input and micro running off the same clock and need to phase shift the input so the pulses are centered over Q2 and Q4.

[Ian.M]

However, that's without the prescaler.  With the prescaler enabled 8 bit PIC T0CKI inputs are typically good up to 50MHz, for 50% dutycycle squarewave input provided your Fosc is high enough to meet the 4Tosc + 40 ns constraint after division by the prescaler.  at 256:1, any clock above 200KHz will do.

Add an external fast D type flipflop in front of T0CKI wired for divide by 2 to guarantee 50% duty cyle with its /CLR input driven by a CCP pin for a hardware gate, and its /SET pin driven by an I/O pin so you can toggle to clock the prescaler till the next Timer 0 LSBb transition, and you can use Timer 0 of a PIC18 as a 24 bit counter to implement a 7 digit  100MHz frequency counter.

[KL27x]

^I know better than to question you, but what you just wrote seems to contradict:

This determines the minimum value of the pulse width that enters through the T0CKI pin. The minimum time period of the input clock pulse is, therefore, 4Tosc + 40 ns, and the maximum frequency will be the reciprocal of this.

Well, I suppose as long as prescaler is off.

To date, I always thought the prescaler acted as a frequency divider. Just dividing the resulting count by multiples or 2, up to 256x. Same thing as the post scaler, essentially. Now I see that would be kinda redundant. I mean you could just have more post scalers. I guess you would just call the scalers, lol. 

My brain just exploded.   Shouldn't there be analogous information regarding frequency or timebase maximums for the prescaler, then? I trust you are right, mind you. I'm just wondering if I missed this info in the datasheet or if it's not there.

If the prescaler will capture shorter ticks asyncronously, then, regardless of the oscillator... so at the cost of loss of a wee bit of absolute resolution, setting the prescaler to 2:1 would seem to be a good idea in general, then? Hmmm...

[NorthGuy]

To date, I always thought the prescaler acted as a frequency divider. Just dividing the resulting count by multiples or 2, up to 256x. Same thing as the post scaler, essentially. Now I see that would be kinda redundant. I mean you could just have more post scalers. I guess you would just call the scalers, lol. 

Prescaler is a separate physical device which is asynchronous to the CPU clock (or any other clock). Therefore, it can work at higher frequencies. 50 MHz is in most datasheets in the AC characteristics section (10 ns pulse width is the characteristic you want). The output of the prescaler goes to the timer. Some of the timers can be driven directly by the prescaler (async mode). Alternativey timer may use CPU clock to sample the prescaler input (sync mode).

[Ian.M]

It always helps  be able to consult the specific device datasheet so I hope Khatas is going to stop being coy about which PIC he's using.  We know its an 8 bit one because none of the others have four clock cycles per instruction, but at the moment, unless someone recognises the exact text of the quote to narrow down the family all we know is its a PIC 10/12/16 or 18.

Microchip aplication note AN592 Frequency Counter Using PIC16C5x
is worth a look to see the basic technique of manually clocking the prescaler to determine its count to get 8 bits extra resolution for Timer 0.     As the only 8 bit PICs with a 16 bit Timer 0 are PIC18, it obviously makes sense to use that family for PIC frequency meter designs - I mentioned above that effectively gives you a 24 bit timer.

And NO, before anyone asks, 16 bit Timers 1,3,5 etc. don't have a TxCKI that can accept a 50MHz signal.  Check specific datasheets for details but they are a lot more limited.

If you are building a frequency counter, its advisable to also route the input to a CCP pin for low frequency operation to avoid the need for ridiculously long gate times by implementing period measurement in hardware, then taking the reciprocal to get the frequency.  Depending on Fosc, that may be preferable up to maybe 10KHz input frequency.