IIRC, most of the discrepancies in recommended nMCLR/Vpp 'isolation' circuits were due to Microchip's transition from EPROM (OTP unless in windowed CERDIP) to FLASH program memory in their MCUs. Their EPROM technology did not use an on-chip charge pump for the programming voltage, so programmers of that era had to supply significant current to the Vpp pin during programming (e.g. for PIC18C452, max. 50mA), which meant it had a robust pin driver circuit, capable of charging/discharging a moderate value external reset timing capacitor quickly. The diode was problematic because it effectively floated the /MCLR pin during the reset pulse. It worked if there was enough diode junction capacitance to keep the pin low long enough. This was before the introduction of an internal weak pullup for /MCLR.
With FLASH PICs, came the introduction of low cost programmers and debuggers, Microchip's PICkit and ICD. Neither had strong /MCLR pin drivers as the new technology used an on-chip charge pump to get the required bias voltages for programming the FLASH memory array, relegating the 'Vpp' supply to only being a control input. They were much less tolerant of reset pin capacitance, which compounded a design error* in the earliest FLASH PCs which used the same program counter for programming as they did when running, so slowly rising /MCLR with a clock source present could result in the program counter incrementing between the chip exiting /MCLR RESET and reaching the Vpp threshold to enter programming mode, resulting in the program being written to the memory at an incorrect address, off by one (or more) locations. To get fast enough nMCLR/Vpp edges, diodes were no longer acceptable so the recommendation shifted to using a nominally 5K isolation resistor between /MCLR and any RC reset circuit as all ICSP capable programmers of that era were specced to be able to drive a 5K load on /MCLR. 4K7 was the generally 'close enough' value actually used.
The recommendation for a simple 10K pullup to Vdd, *NO* RC reset circuit or isolation circuit came with the introduction of internal reset timers, and was permissible as all programmers had target buffers or other circuits that would draw at least 1mA from Vdd_target, so the max. Vpp programming voltage of 13V couldn't drive enough current through the pullup to cause Vdd to rise out of spec.
* To resolve this bug in later devices, programming mode entry was made to perform a hardware reset.
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