PIC18F4553 - analog layout

[poorchava]

Hey,

I'm designing a power supply around PIC18F4553, which I chose because of 12-bit ADC it has. Other than ADC, it's identical to popular 18F4550. What bugs me is that this chip doesn't have separate pins for analog power (like AVSS and AVDD in dsPICs).

I'm afraid, that the 12-bit resolution of the ADC can be useless, because of noise on digital lines. Of course I have used plenty of decoupling caps, but i don't know if it will be enough.

Any hints?

[jahonen]

Use a hefty contiguous ground plane, it works wonders for the noise immunity. If your ground system is not stiff enough, you can't get clean analog signals, whatever you do. That's why Jim Williams liked to use that copper clad construction for his prototypes.

Regards,
Janne

[PA0PBZ]

REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1

bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD

[Mechatrommer]

If your ground system is not stiff enough, you can't get clean analog signals, whatever you do.

precious advice! but what does it mean by "stiff"? punching few vias or through holes will not make it stiff? i find it quite impossible to get a contigous ground plane with 2 layers only board (i'm refering to my diff probe i currently do)



i tried to make the ground plane to the left of picture (under and surrounding the text "soasystem.com") as hefty as i can, avoid any possible route on the bottom layer, but through hole parts simply screw that up. what do you think janne from your experience, is that hefty enough? or 50% or 30% hefty?

[jahonen]

precious advice! but what does it mean by "stiff"? punching few vias or through holes will not make it stiff? i find it quite impossible to get a contigous ground plane with 2 layers only board (i'm refering to my diff probe i currently do)

i tried to make the ground plane to the left of picture (under and surrounding the text "soasystem.com") as hefty as i can, avoid any possible route on the bottom layer, but through hole parts simply screw that up. what do you think janne from your experience, is that hefty enough? or 50% or 30% hefty?

By heftiness I mean that the ground plane should be as solid as possible, to lower its impedance. Lower the impedance, less differences of ground potentials between components connected to it, when currents flow in ground plane. A solid plane is superior in many ways compared to having just some ground traces. Or if one has a multilayer board, more ground planes one can afford, the better. And yes,  it is relatively difficult to maintain good planes with just two layers, but it of course depends how much time one can spend optimizing the layout.

I think you can estimate the heftiness by using that criteria. Its pretty hard to remotely estimate the heftiness without deeper knowledge of the circuit and requirements, but at least the plane at the centre of your pcb looks certainly ok'ish. Combining analog and digital creates steeper requirements (or even combining "normal" logic and PECL, PECL uses VCC as a reference and normal logic tends to make it noisy), since high currents in digital section easily spoil the analog signals if one is not careful. Having a ground plane makes it easier to filter the analog signals. This filtering fails to work properly if ground is not hefty enough.

Regards,
Janne

[poorchava]

Maybe I should've added a few more words about my application.

Transformer outputs 24VAC and 7.5VAC. 24VAC is rectified and filtered giving ~31VDC, which supplies power darlington and also is fed to LM317L. LM317 outputs around 27VDC (positive opamp supply). 7.5VAC is rectified, filtered and passed through a standard 7805, to supply MCU. This 5V is then fed through an LC filter making up analog +5V(for eg. DAC which doesn't have split supply), which in turn is fed into TC7660 charge pump to produce -5V (negative opamp supply). So in my circuit i have: unregulated 31V, regulated 27V, digital +5V, analog+5V and analog -5V.

I wonder if it makes sense to filter charge pump output with and inductor + another capacitor. I am also powering the charge pump from analog voltage, maybe i should power it from digital one, and then LC-filter +27V, +5V analog and -5V analog?

As for ground planes, i usually tend to place and route everything on top layer. In general it's easiest to place decoupling caps and route power supplies on bottom layer. I generally fill all empty space with GND copper pour on both top and bottom and switch HEAVILY with randomly placed vias (by randomly i mean by hand and not in regular distances)

[Neilm]

Allow space for multiple decoupling caps in as small a package as you can use. I would suggest 3 caps, one 100pF or so, one 10nF and one 100nF. They will have different filtering effects and will squash a larger range of unwanted signals. Ensure that the smallest cap is closest to the pins.

Neil

[poorchava]

That is exactly what I'm doing. I generally tend to place 2 in parallel where i expect noise problems. In general one is always typical 100nF, and the other depends on situation, mostly using 10uF (is voltage is low enough for ceramic 10uF 0805 cap), 1nF or 100pF. I'm wondering about inductance value.

I also want to place a 1812 size 47uH 140mA smd ferrite choke on both -5V and +27V rails near the opamp, forming an LC filter with -3dB frequency at ~100kHz. I suppose this will be enough to suppress any digital noise. If i aim for 10kHz, the inductors and capacitors become kinda massive . I will use separate inductors near all chips using 5V analog supply and also similar one (but i guess a bit higher current rating) on MCU supply. I wonder if this will be enough. I mean empty unpopulated footprints don't cost anything apart from PCB space