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PIC18F4553 - analog layout

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poorchava:
Hey,

I'm designing a power supply around PIC18F4553, which I chose because of 12-bit ADC it has. Other than ADC, it's identical to popular 18F4550. What bugs me is that this chip doesn't have separate pins for analog power (like AVSS and AVDD in dsPICs).

I'm afraid, that the 12-bit resolution of the ADC can be useless, because of noise on digital lines. Of course I have used plenty of decoupling caps, but i don't know if it will be enough.

Any hints?

jahonen:
Use a hefty contiguous ground plane, it works wonders for the noise immunity. If your ground system is not stiff enough, you can't get clean analog signals, whatever you do. That's why Jim Williams liked to use that copper clad construction for his prototypes.

Regards,
Janne

PA0PBZ:
REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1

bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD

Mechatrommer:

--- Quote from: jahonen on November 11, 2012, 11:35:08 am ---If your ground system is not stiff enough, you can't get clean analog signals, whatever you do.
--- End quote ---
precious advice! but what does it mean by "stiff"? punching few vias or through holes will not make it stiff? i find it quite impossible to get a contigous ground plane with 2 layers only board (i'm refering to my diff probe i currently do)



i tried to make the ground plane to the left of picture (under and surrounding the text "soasystem.com") as hefty as i can, avoid any possible route on the bottom layer, but through hole parts simply screw that up. :-\ what do you think janne from your experience, is that hefty enough? or 50% or 30% hefty?

jahonen:

--- Quote from: Mechatrommer on November 11, 2012, 12:11:02 pm ---precious advice! but what does it mean by "stiff"? punching few vias or through holes will not make it stiff? i find it quite impossible to get a contigous ground plane with 2 layers only board (i'm refering to my diff probe i currently do)

i tried to make the ground plane to the left of picture (under and surrounding the text "soasystem.com") as hefty as i can, avoid any possible route on the bottom layer, but through hole parts simply screw that up. :-\ what do you think janne from your experience, is that hefty enough? or 50% or 30% hefty?

--- End quote ---

By heftiness I mean that the ground plane should be as solid as possible, to lower its impedance. Lower the impedance, less differences of ground potentials between components connected to it, when currents flow in ground plane. A solid plane is superior in many ways compared to having just some ground traces. Or if one has a multilayer board, more ground planes one can afford, the better. And yes,  it is relatively difficult to maintain good planes with just two layers, but it of course depends how much time one can spend optimizing the layout.

I think you can estimate the heftiness by using that criteria. Its pretty hard to remotely estimate the heftiness without deeper knowledge of the circuit and requirements, but at least the plane at the centre of your pcb looks certainly ok'ish. Combining analog and digital creates steeper requirements (or even combining "normal" logic and PECL, PECL uses VCC as a reference and normal logic tends to make it noisy), since high currents in digital section easily spoil the analog signals if one is not careful. Having a ground plane makes it easier to filter the analog signals. This filtering fails to work properly if ground is not hefty enough.

Regards,
Janne

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