Values coming back mid scale. Changing slightly as input goes from zero to Vdd.
setup
TRISA = 0xffbf; // 1111 1111 1011 1111 // RA6 output (pwm)
TRISB = 0x0f7f; // 0000 1111 0111 1111 // RB12,13,14,15,7 output
ANSA = 0x000d; // 0000 0000 0000 1101 RA0 RA2 RA3 analog inputs
ANSB = 0x0003; // 0000 0000 0000 0011 RB0 RB1 analog inputs
AD1CON2 = 0x0800; // 0000 1000 0000 0000
AD1CON1 = 0x0400; // 0000 0100 0000 0000 conv starts with samp bit clear, 12 bit operation
// abs decimal result unsigned right justified
// AD1CON2 ,AD1CON3 default 0 values OK
AD1CON3 - 0x0000;
bit_set(AD1CON1,15); // turn on converter
// Call
unsigned int read_AD(unsigned int channel)
{
bit_clear(AD1CON1,15); // turn off converter
AD1CHS = 14; // channel & 0x000f;
bit_set(AD1CON1,15); // turn on converter
AD_SampStart(); // #define AD_SampStart() bit_set(AD1CON1,1)
delay_cycles(10);
AD_ConvStart(); // #define AD_ConvStart() bit_clear(AD1CON1,1)
delay_cycles(3);
do{}while(AD_Converting); // #define AD_Converting (!bit_test(AD1CON1,0))
return ADC1BUF14;
}
Thanks