PIC32MX, no change in speed when clock multipliers are changed

[Aethelstan]

Hi, I have a PIC32MX board with an 8MHz crystal and I am testing it by flashing some LED's. The output ports are behaving as expected, however the configuration bits seem to have no effect on my delay when altering the clock multipliers and dividers, leading me to believe that the configuration bits are either not working or it is using a different clock. The crystal is connected to OSC1 and OSC2, and my delay is simply an empty for loop and hence the delay should change as I alter the dividers/multipliers. I have used the configuration bits tool that is built into MPLAB. I am obviously misunderstanding what I am supposed to be doing, but as far as I can tell from the datasheet and other documentation, I have it set up correctly.  The PLL input divider is set to 2, so that the PLL is running at 4MHz. I then use x24 for the PLL multiplier, taking it to 96MHz, then divide again by 4 using the USB PLL divider to go to 24MHz. I think the 96MHz is the actual system clock in this case? I have also tried lower multipliers such as 8 and 16, but the for loop delay sticks dead on 46ms. Any ideas what I am doing wrong?

Code: [Select]

#pragma config PMDL1WAY = ON            // Peripheral Module Disable Configuration (Allow only one reconfiguration)
#pragma config IOL1WAY = ON             // Peripheral Pin Select Configuration (Allow only one reconfiguration)
#pragma config FUSBIDIO = OFF           // USB USID Selection (Controlled by the USB Module)
#pragma config FVBUSONIO = OFF          // USB VBUS ON Selection (Controlled by USB Module)

// DEVCFG2
#pragma config FPLLIDIV = DIV_2         // PLL Input Divider (2x Divider)
#pragma config FPLLMUL = MUL_24         // PLL Multiplier (24x Multiplier)
#pragma config UPLLIDIV = DIV_4        // USB PLL Input Divider (4x Divider)
#pragma config UPLLEN = OFF             // USB PLL Enable (Disabled and Bypassed)
#pragma config FPLLODIV = DIV_4         // System PLL Output Clock Divider (PLL Divide by 4)

// DEVCFG1
#pragma config FNOSC = FRCDIV           // Oscillator Selection Bits (Fast RC Osc w/Div-by-N (FRCDIV))
#pragma config FSOSCEN = OFF             // Secondary Oscillator Enable (Disabled)
#pragma config IESO = ON                // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = HS             // Primary Oscillator Configuration (HS osc mode)
#pragma config OSCIOFNC = OFF           // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FPBDIV = DIV_8           // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/8)
#pragma config FCKSM = CSDCMD           // Clock Switching and Monitor Selection (Clock Switch Disable, FSCM Disabled)
#pragma config WDTPS = PS1048576        // Watchdog Timer Postscaler (1:1048576)
#pragma config WINDIS = OFF             // Watchdog Timer Window Enable (Watchdog Timer is in Non-Window Mode)
#pragma config FWDTEN = ON              // Watchdog Timer Enable (WDT Enabled)
#pragma config FWDTWINSZ = WINSZ_25     // Watchdog Timer Window Size (Window Size is 25%)

// DEVCFG0
#pragma config JTAGEN = OFF              // JTAG Enable (JTAG Port Disabled)
#pragma config ICESEL = ICS_PGx1        // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
#pragma config PWP = OFF                // Program Flash Write Protect (Disable)
#pragma config BWP = OFF                // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF                 // Code Protect (Protection Disabled)
Thank you

[NorthGuy]

Your clock is set to FRCDIV, so it doesn't use neither crystal nor PLL. Since your clock switches are disabled, you cannot change to PLL at run time if you try.

[Aethelstan]

Thank you! I have made a change to primary oscillator with PLL and it now behaves as expected