Cyclone V SoC usage and fun projects.

[TiN]

Hope you can share my excitement, as I should be getting Digikey box tomorrow, with brand new Terasic DE1-SoC with that fancy ALTERA (or should I say now Intel?) FPGA+ARM Cyclone V.



I have and used few older Terasic boards before, like Cyclone II DK20 and DE0-nano (MAX2 2210), so choice for Cyclone V was straightforward.
My main intention for this is to have it run linux on ARM side, try to get linux-gpib working on it and use FPGA to talk with various analog stuff.
Linear DAC board is coming same box as well, and I'll try generating some precision AC with help of it.

Never used these new ARM&FPGAs chips before, so if you have something to say about 'em or interesting projects - feel free to tell.
Eventually I'll have ADCs and some front-ends made for it to make it into some usable lab tool. Perhaps with an LVDS panel as well.

[crispus]

How does the fpga communicate with the arm CPU? At what speed?

[Berni]

I have a similar board.

I was not very interested in linux, but you do get very tight connectivity between the FPGA fabric and the SOC core. You get a bus from the internal memory switch matrix for both master and slave. So not only can the ARM have a part of its memory space point in to the FPGA fabric you can also have the FPGA fabric write the memory space of the SOCs peripherals. On top of that you get another very wide and high troughput bus directly to the SOCs DDR memory controller. That way both the ARM and FPGA can share a single block of DDR3 memory without any performance penalties apart from having to share bandwidth. being able to share memory like that is probably very useful for making FPGA coprocessors since you don't need to copy the data it needs in to its own memory.

[TiN]

Got the board and DAC demo kit.

 

Paper datasheet, whoa . Demoboard is based on LTC1668, 50MSPS 16bit DAC with parallel interface. Perfect slave for DE1-SoC.



Closeups:



Output front end using signal transformer, but that will likely be gone, as I need DC accurate outputs too for calibration.



+1 never-ending project into already long list? 

[Rasz]

what is the deal with those weird stitched ground pads? what is the purpose of the gap in the middle?

[Berni]

what is the deal with those weird stitched ground pads? what is the purpose of the gap in the middle?

Its a fairly pornographic ground plane split between digital and analog ground. It lets you join the grounds on various points if you want or it can probably also be quite useful for probing signals at the chip to get a very tight short ground path.

Lovely looking board in my opinion, lots of attention to detail that you don't always see in eval boards. What plans do you have for that fancy DAC chip?

[TiN]

I failed to see how 8365 NTD (266$ USD) on Terasic site is any cheaper than 249.9$ from Digikey.
Also it has flag "Contact us" instead of simple adding to cart, so no, thank you. 

[Rasz]

what is the deal with those weird stitched ground pads? what is the purpose of the gap in the middle?

Its a fairly pornographic ground plane split between digital and analog ground. It lets you join the grounds on various points if you want or it can probably also be quite useful for probing signals at the chip to get a very tight short ground path.

those gap tracks start and end shorted, so whats the point?

[TiN]

I plan to build calculable AC voltage source using this DAC eval kit, DE1-SoC and linux-gpib with 3458A as calibration reference.

[TiN]

Step 0, get linux-gpib working on DE1-SoC..



Done. Made up somewhat ugly article about the process. I'm sure some linux guru's could straighten it up many fold... 

Step 1, get GPIO, I2C and SPI working from HPS

In progress...

Step 2, test speed for GPIO

TBD...