Peel's have foldback from out to in.
The. Altera 600 was originally an intel device.
300 310 600 610 900 910 were intel pld's. that division was sold to altera . Its direct offspring is the max family.
AMD did the same with their Mach devices. Mach 200 210 400 410 .. See a pattern there ?
Intel sold to altera, amd sold to lattice. MMI was inventor of Pal, fabbed at ti, Lattice was the inventor of GAL. They fabbed at ST.
This architecture later became what is now known a CPLD.
Essentially a bunch of PAL (MMI trademark) or GAL (ST / lattice trademark) on a same die with an additional i terconnect matrix between em.
A pal or gal is essentially a gatecloud , possibly followed by registers. (Not all pals have fliplflops , they can be pure and/ or / not clusters)
As a reult there is no, or very limited(gal/peel) feedback from the last output to the interconnect matrix. the cluster outputs connect to the pin of the chip.
Cplds solve that problem by having an additional interconnect matrix between the cloud output and the pins.
In a pal or gal the cloud output goes directly to a, fixed, pin. You can't reroute output 7 to pin 3... Some adjacent pin swaps are possible but it is not truly random. Cplds solve that by having an interconnect grid between the clouds and the outputs.
In simple pld's there is one flipflop per pin. So a 40 pin device could have 32 flipflops (basically four pal's. a pal thpically had either none, 4 or 8 flipflops). There were no buried flipflops.
Cpld allowed buried flipflops. Essentially a pal that is not routed to io
Hierarchy( complexitiy)
Combinatorial pal. And or not only, no feedback
Registered pal. Adds Registers, no feedback
Gal .reprogrammable (pal is OTP)
Peel feedback
Pld . Cloud of pals. Interconnect on input, feedback , but no interconnect on output. One flipflop per pin
Cpld , cloud of pals , interconnect on input and output, buried pals (more flipflops than pins.)
The problem with such an architecture is that it is extremely wasteful. The routing is so limited and you waste too much logi in the combinatorial cloud. The granularity is too high.
Fpga solves that. There the combinatorial cloud is smaller and there are only 2 or 4 flipflops per block.
This is called a macrocell. You can see a macrocell as half a peel. Basically 2 or 4 flipflops with feedback into the matrix. Then there are short interconnects between adjacent macrocells, intermediates that hop 2 or 4 macrocells far. This makes a cluster of macrocells called macroblock.
A large interconnect grid then connects neighbouring macroblocks 1 2 or 4 hops. Macroblocks are arranged in stripes vertically or horizontally. The you have large raceways interconnecting the columns
Waferscale took the cpld and slapped on ram and eprom eeprom to essentially make the ipsd.
Take cpu of choice, config the logic to do address decoding and io and some simple functions. Load code in eeprom and go. Two chip solution. Cpu and an ipsd.
All gone the way of the wind ... I had an mmi databook in 1986.. The software was a 51/4 inch 360 floppy for dos.
You had to make a textfile with stars and dots. A star was a blown fuse.... They had drawings with rows and columns..
It was like orcad for dos making linrary symbols with the star and dot thingie....
Meanwhile Actel came up with the pga programmable gate array. This was antifuse technology for the military. Xilinx replaced the antifuse with ram and fpga was born...
Altera kickstarted due to intel seeding them their cpld line
The xilinx tools originally were. Schematic entry. Viewdraw and viewlogic on early sun workstations.
Altera used daisycad as an entry tool.
Orcad stepped in the pal and gal config with orcad pld...
Wow... Talk about a trip down memory lane.....
Now kids come out of school barely know what is a nand gate, let alone knowing you can have four of those in a 7400 ttl chip... They stare at you .:Wtf is a ttl ? Vhdl we have heard of ...
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