The Raspberry PI PICO 2, now has extra RISC-V cores

[MK14]

https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/

Raspberry Pi Pico 2 lands with (drum roll) RISC-V cores

It's exciting news for RISC-V fans: Raspberry Pi is adding support for the open ISA with the launch of the Pico 2 and the company's new RP2350 microcontroller.
Pi Pico 2

The Pi Pico 2 that arrived at a seaside Vulture outpost today – click to enlarge

The Pico 2 board retails for $5 and, according to the Pi team, retains backwards hardware and software compatibility with previous versions. While the on-chip memory has been upped to 520KB – there is also 4 MB of on-board QSPI flash – the two RISC-V Hazard3 CPU cores included in the microcontroller may well interest enthusiasts and implementers alike.

The Hazard3 cores are optional: Users can at boot time select a pair of included Arm Cortex-M33 cores to run, or the pair of Hazard3 cores. Both options run at 150 MHz. The more bold could try running one RV and one Arm core together rather than two RV or two Arm.

Hazard3 is an open source design, and all the materials for it are here. It's a lightweight three-stage in-order RV32IMACZb* machine, which means it supports the base 32-bit RISC-V ISA with support for multiplication and division in hardware, atomic instructions, bit manipulation, and more.

Pi supremo Eben Upton told The Register, "RISC-V is an exciting development for us: Our goal is to give software developers a chance to experiment with a different architecture in a stable, well-supported environment, and to express our enthusiasm for the Hazard3 open-hardware core, which was developed by Luke Wren, one of our ASIC engineers, in his spare time.

"I think RISC-V provides researchers with an interesting environment for architectural experimentation, and SoC designers with a high degree of configurability. One contribution we're making here is to legitimize Hazard3 as a mature, 'clean' core for verbatim use in other designs, or as a basis for further development."

As for leaping into the world of RISC-V, Upton explained how the cores would work: "They're selectable at boot time: Each port into the bus fabric can be connected either to an M33 or a Hazard3 via a mux. You can even, if you're feeling obtuse, run with one of each."

Hazard3 is a modest but capable microcontroller-grade design. It's not for running a modern general-purpose operating system on. Then again, that's not really the point of the Pico 2 and the RP2350.

Upton told us: "FreeRTOS is the preferred OS (as on RP2040). There's an increasing amount of excitement around Zephyr, and some community effort to port that to the RP2 platform, and we may engage formally with that in due course."

As with the original Pico, there are 26 multi-purpose GPIO pins, though the jump from 264KB of SRAM and 2MB of onboard flash opens the device up to more intriguing development options. Aside from the obvious, "Does it run Doom?" question – the answer is yes – the RP2040 on the original Pico has been pressed into service by the emulation community, not forgetting the recent implementation of Apple's original Mac on the device.
Security

The Pico has also turned up in smart home implementations and proven popular with industry, although perhaps not as popular as the team would like.

Some users have described the security features, or lack thereof, of the RP2040 as enough to make it a non-starter in the embedded world; they want to keep their proprietary code on the device away from reverse engineers, and the RP2040 doesn't help with that.
Raspberry Pi Pico 2

Extra detail - click to enlarge

To that end, the Raspberry Pi team has implemented what it calls a "comprehensive security architecture" into the new microcontroller. This is built around Arm TrustZone for Cortex-M and incorporates signed boot, 8KB of antifuse OTP for key storage, SHA-256 acceleration, a hardware TRNG, and fast glitch detectors. There's also secure boot ROM.

According to the Pi team, this will allow "professional users to integrate RP2350, and Raspberry Pi Pico 2, into products with confidence."
Well Arm'd

Upton was keen to emphasize the additional performance on tap. On the Arm side, the Pico has stepped up from two Cortex-M0+ cores to a Cortex-M33 pair, which each have extra bells and whistles including an FPU and DSP.

"The extra performance, and particularly floating point and DSP performance, opens up a bunch of new applications, both for hobbyists and professional users," he said of the Pico 2.

"Some of our music synth customers (we have a surprisingly large number of these) are quite excited about the things they'll be able to do with the platform."

However, he noted, "The security and low-power features are probably as interesting to industrial customers as the additional performance."

The downside to all the improvements is the inevitable price increase – the Pico started at $4, and the Pico 2 is slated to begin at $5. While unlikely to worry enthusiasts too much, the price increase could concern customers buying in bulk.

The Pico 2 also lacks some of its predecessor's connectivity options – a Wi-Fi version is not yet available. However, Upton told us that one would arrive "likely before the end of the year."

Getting hold of one could also be tricky. Upton told us that "this is going to be a pretty shallowly stocked launch," with more volume set to come through in the next few weeks. The price increase was attributed to cost growth in the platform and a slightly more expensive chip – the RP2350 is $0.10 more than the RP2040.

And the number? Sadly nothing to do with the Amiga 2000's 2350 genlock, but instead derived from the basic chip itself. As Upton explained: "2350 = 2x Cortex-M33s, with 2^5*16KB of SRAM and 0KB of Flash.

"The 0 indicates the chip itself has no Flash included. In this generation we'll be offering an RP2354 variant which includes 2MB (=2^4*128KB) of in-package QSPI Flash."

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As for how the hardware and software compatibility works, Upton told us, "Pretty much everything should work, though it's a case of recompiling rather than just deploying the same binary."

While the microcontroller business represents a tiny percentage of Raspberry Pi's revenue, its volume is becoming substantial.

The price increase may be a shame for some, though there is that additional processing oomph on offer. The arrival of RISC-V in Hazard3 form makes the Pi Pico 2 intriguing from both a hobbyist and an industry perspective.

It will be very interesting to see what customers make of it. ®

[Jope]

This guy had access to samples over the last year: Why you should fall in love with the RP2350

[ataradov]

Yes, using two toolchains at the same time is exactly what I want. I guess they wanted to have a smooth transition to RISC-V, but the device is bizarre.

And one again, only 30 GPIO on a 60-pin device.

[coppice]

And one again, only 30 GPIO on a 60-pin device.

That does seem a bit thin. What's extra odd is the 60 pin version has 30 GPIOs, but the 80 pin version only has an additional 18. They use 2 extra VDD pins. This kind of thing may be a trend, though. With a lot of MCUs booting or running from QSPI that chews up a few pins. More complex split rails for a fine geometry die chews up a few pins. The trend towards new MCUs have a GPIO capability on everything but the power pins might be over for anything but a tiny package...... unless there is a customer backlash.

[langwadt]

Yes, using two toolchains at the same time is exactly what I want. I guess they wanted to have a smooth transition to RISC-V, but the device is bizarre.

And one again, only 30 GPIO on a 60-pin device.

seem like the intention is that you pick tool chain you prefer and just use that

it does show that cpu cores take up hardly any area, it's all RAM and peripherals

[Rudolph Riedel]

Briefly checked the datasheet - https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf - if that thing is supported by PlatformIO some day and I get a free board, maybe I let it run some SPI code.

And RISC-V?
I find that extremely boring from a developer point of view.
The core is something for the compiler to deal with, at least for the most part.

Edit: and again, no f*ing reset button and a micro-usb connector.

[iMo]

Sparkfun offers one with a linear voltage regulator.. nice..
And with USB-C and 2 buttons - the boot and the reset too..
https://www.sparkfun.com/products/24870

PS: and ie. the Waveshare Electronics will follow soon, my bet (the same setup but cheaper)..

[SiliconWizard]

Yes, using two toolchains at the same time is exactly what I want. I guess they wanted to have a smooth transition to RISC-V, but the device is bizarre.

And one again, only 30 GPIO on a 60-pin device.

They have a 48-GPIO version: https://www.raspberrypi.com/products/rp2350/
not sure why so many pins for so few GPIOs though. That's a minus point. Other than this, the "dual boot" thing is baroque indeed (reminds me of the SG2000 on the milkV duo 256M). Yes, that looks like the addition that was probably cheap enough to include while trying to please everyone.

But otherwise, the updates are cool. A second USB controller could have been good.

[tszaboo]

Yes, using two toolchains at the same time is exactly what I want. I guess they wanted to have a smooth transition to RISC-V, but the device is bizarre.

And one again, only 30 GPIO on a 60-pin device.

They have a 48-GPIO version: https://www.raspberrypi.com/products/rp2350/
not sure why so many pins for so few GPIOs though. That's a minus point. Other than this, the "dual boot" thing is baroque indeed (reminds me of the SG2000 on the milkV duo 256M). Yes, that looks like the addition that was probably cheap enough to include while trying to please everyone.

But otherwise, the updates are cool. A second USB controller could have been good.

The RPi team for sure has an overzealous signal integrity guy. It shows on all designs. The Pi Pico has GND pin every 4 pad, the RP2040 has a bunch of power supply bypassing pins, while a comparable STM32G0 has total of two power supply pins. The USB is impedance matched for USB 1.1 speeds, with thin PCB and thick traces. for like a 10mm length. 
I've run 300mm long USB traces with whatever thickness and stackup, and it just works.
The end result is that it's a mayor PITA to layout the RP2040 with 0402 or larger components.

A few things they don't talk about. The datasheet is twice as long. It has a core voltage DC-DC. New pinout. This also will want 0201 capacitors. Power consumption in sleep is still pretty bad, ~50uA in lowest power states. That's probably already good enough for rechargeable batteries, and it's an improvement over the quite laughable RP2040 sleep currents.

So what am I missing? The built in Flash still. Makes making a custom board PITA, as you either use the exact same flash or you have to compile micropython yourself (yuck). Built in tunable crystal loading capacitors. Same for the USB line resistors, maybe a second USB, though a I recall you can make that with the PIO somehow.

[ataradov]

The RPi team for sure has an overzealous signal integrity guy.

Or inability to meet the requirements without going overboard, which is more likely, IMO.

[SiliconWizard]

Yep. Anyway, we're criticizing the new RP2350 but I'm sure we'll find fun/interesting uses for it. As it was the case when the 2040 was announced.

But yes, it's still more of an educational chip than something really competitive (apart from pricing).

For the next iteration, I was hoping for more GPIOs yet, the performance upgrade is not bad, but I would have liked a higher Fmax (and while the RP2040 has a wide overclocking margin, with the M33 cores, I'm not sure it will overclock as well). As I said, possibly a second USB controller. As to the PIO, they added a 3rd unit and added some features, but I would have liked an increased program memory, apparently still the same.

The RISC-V cores don't look too bad in terms of performance - about 3.8 Coremark/MHz, which is better than most RISC-V-based MCUs out there.

[floobydust]

I keep looking for general purpose timers, you know the kind that can do an input capture based on external input, the kind every other MCU has.
RPI Foundation seems to know little about the requirements for embedded systems and these MCU's focus on the OS, there's a 64-bit usec tick timer.
More cores, great - but I think the design team missed the boat again. Yeah I know the PWM state machine and a bunch of hoops sorta works if you don't need accuracy.
It's not yet out what the TPU can do, if it's the same etc.
https://datasheets.raspberrypi.com/rp2350/rp2350-product-brief.pdf

[ataradov]

More USBs will come at a price of fewer pins until they can figure out how to multiplex them with GPIO pins. They really need to start figuring out the multiplexing part. Too many pins end up being dedicated  single function.

[brucehoult]

Yes, using two toolchains at the same time is exactly what I want.

GCC is GCC ... just change the triple. Obviously all the peripherals stay the same, at the same addresses, no matter which CPU you use, so presumably the same headers work on either ISA.

A bit of a shame that the Arm cores now have DP FPU and even I think SIMD, while they've used a RISC-V core with neither and has slightly lower Coremark too, so most people will ignore them.

Huge upgrade from the CM0s on the Arm side, at least.

That guy who's been using prototypes for a year says you can add a lot of external RAM (16 MB I think he used) and it works without issues, even with both stack and PC out in that RAM, so that's cool.

[MK14]

A bit of a shame that the Arm cores now have DP FPU and even I think SIMD, while they've used a RISC-V core with neither and has slightly lower Coremark too, so most people will ignore them.

It seems that was NOT an option, unfortunately.

Amazingly, the floating point double, is implemented, by only using a few thousand, more transistors.

But in order to do that, it couldn't have a high speed multiplier (without greatly exceeding that small transistor budget).  So, it 'cheats' and uses the Arms (M33F), (integer very high speed multiplier) one (via the Arm M33F custom instruction option, I think), to allow, relatively fast double floating point (multiply) calculations.

(Presumably) That was not an option with the RISC-V core.  Possibly because of the communications route (using the custom Arm instruction features), between the double floating point hardware, and the Arm M33F hardware, not being available when RISC-V is enabled as an option, hence disabling the Arm M33F core(s).

[SiliconWizard]

That guy who's been using prototypes for a year says you can add a lot of external RAM (16 MB I think he used) and it works without issues, even with both stack and PC out in that RAM, so that's cool.

Well, yeah, QSPI PSRAM. I got about 30 MBytes/s sustained on a iMXRT1062 with PSRAM, I'd expect even lower throughput with the RP2350. Cool for some extra RAM, but relatively slow. Goes through cache though, so may be ok if you work on relatively small datasets at a time.

From what I've seen in the DS, they have added a second chip select, so now you can use a Flash chip AND a PSRAM chip. They share the same QSPI controller. Don't expect miracles in terms of bandwidth.

As to the RISC-V cores, it's that: https://github.com/Wren6991/Hazard3
It doesn't contain any FPU. Adding one from an external project should be doable, although with some work and especially verification work. Probably something that the RPi didn't care to do.

[SpacedCowboy]

For the next iteration, I was hoping for more GPIOs yet, the performance upgrade is not bad, but I would have liked a higher Fmax (and while the RP2040 has a wide overclocking margin, with the M33 cores, I'm not sure it will overclock as well). As I said, possibly a second USB controller. As to the PIO, they added a 3rd unit and added some features, but I would have liked an increased program memory, apparently still the same.

A few points.

• There's a guy who's been beta-testing it for about a year now, and he says the overclocking is just as impressive - he's never had any problems running at 300MHz.
• Using HyperRAM, you can get 42 write, 32 read on an RP2040. I expect the RP235x to be broadly similar. Slightly faster than that iMXRT1062, at least for writes
• There's a fast (TX only, sadly) 8-bit parallel port @ 2400Mbit/sec  which has a crossbar that can be fed by the PIO, and can reformat data for TMDS
• The PIOs got a major upgrade with the ability for a PIO to signal/interrupt another which makes far more complex stuff viable, and also with the ability to read/write directly into the PIO FIFO, treating it as RAM, so you have a lot more options in terms of data transfer
• DMA got an upgrade with infinite re-triggering (no longer need to use another DMA channel to re-trigger), and more offset choices for repeated triggering
• ADCs are less noisy now
• GPIO is 5v-tolerant, which is nice for me, YMMV
• signed boot, OTP storage for encryption key, encrypted bitstream stored in the on-board flash makes it more palatable for commercial use
• Half a meg of RAM is a nice upgrade
• dual-core M33's which (as above) overclock significantly
• An extra 18 GPIOs, +2 if you want to use the USB pins +6 if you can download to RAM via SWD and want to use the QSPI pins
• Co-processor interface to GPIO, so a single instruction can write up to 64 (!) GPIOs without any register / bus latency (yeah, I'm looking at you, STM32H7) getting in the way. Fast GPIO is awesome
  
• guaranteed production until 2040

... all in a $1 chip. Quite an upgrade IMHO.

[edit]
If you really want more (up to 3, I guess) USB ports, you can use PIO to implement low/full-speed USB, and as alluded to above, the existing hard-ip USB pins are in fact available as GPIO, though there are slew-rate restrictions because of the internal pulls.

[MK14]

This (Pimoroni Pico Plus 2) seems an interesting board, which is currently available, and in-stock, for £10 + VAT = £12 + shipping charges. (Rather than the £4 + VAT etc, for the standard PICO 2).

https://shop.pimoroni.com/products/pimoroni-pico-plus-2?variant=42092668289107

They add to the standard PICO 2 board, the following:

USB-C for power, programming, and data transfer, which is more compatible for some peoples setups, than the micro-USB one.
The RP2350B version, which gives the extra I/O pins.
Flash increases to 16MB of QSPI flash supporting XiP (from the standard 4MB).
It has an onboard 8MB of PSRAM.
This one has got a RESET button (Reset and BOOT buttons).
Also some other bits and pieces, like some connectors onboard.

WARNING:
If past experience is anything to go by (i.e. the original PICO).  After about 2 or 3 days after launch (after initial stocks and pre-orders dry up), the new PICO's, may takes ages to get.
But maybe this time around, there will be plenty of availability.  I just don't know.

[shabaz]

This (Pimoroni Pico Plus 2) seems an interesting board, which is currently available, and in-stock

Nice, thanks for spotting that! I've decided to order one, while I wait for the normal Pico 2 boards to become available.

I do find the original RP2040/Pico quite useful (and easy-to-use SDK too), even though (just like the new products) not all makes sense, there's typically plenty of raspberrypi.com weirdness in their product design decisions.

There's some OTP register for the cores, so maybe the RISC-V is to sell to certain customers/regions they might not have a license to sell ARM to? (i.e. if they disable it before selling it). Pure speculation though.. I know zero about semiconductor sales.

[floobydust]

RP2350 Datasheet.pdf 1,347 pgs. so it will be a while before it's really understood well. I got a bit lost on why two different CPU cores are in this thing.

"3.6 The RISC-V processors on RP2350 do not have access to the Cortex-M33 coprocessors"
"3.9. Arm/RISC-V Architecture Switching
RP2350 supports both Arm and RISC-V processor architectures. SDK-based programs which do not contain assembly code typically run unmodified on either architecture by providing the appropriate build flag.
There are two processor sockets on RP2350, referred to as core 0 and core 1 throughout this document. Each socket can be occupied either by a Cortex-M33 processor (implementing the Armv8-M Main architecture, plus extensions) or by a Hazard3 processor (implementing the RV32IMAC architecture, plus extensions)."

"3.9.2. Mixed Architecture Combinations
The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1.
Practical applications for this are limited, since this requires two separate program images. The two cores interoperate normally, including shared exclusives via the global monitor: a shared variable can be safely, concurrently accessed by an Arm processor performing ldrex, strex instructions and a RISC-V processor performing amoadd.w instructions, for example."

[SiliconWizard]

Interesting. While it may have little practical value, being able to run an ARM core alongside a RISC-V core has potentially some educational value.

[MK14]

While it may have little practical value

I'd suspect, their future plans, might be to allow this chip to be versatile enough, to be used as a support chip, for either an all Arm or all RISC-V system.

I.e. This now gives the PI foundation, options to make a new (SBC) with big and powerful Arm cores or big and powerful RISC-V cores, and have this new chip, added to the board, regardless.  Resulting in an overall, all Arm or all RISC-V SBC.

They might also want to test the water, with RISC-V systems.

[josip]

Using it as USB device still need external crystal.

[woofy]

I recall being quite excited when the RP2040 was announced, especially as a long production run was promised, and purchased a PICO module to play with. Since then it has gathered dust in a spares box. It's a great chip but has never been the right fit for any of my professional or hobby projects. The RP2350 looks like a useful incremental improvement, but has not addressed my biggest showstopper - connectivity. Time will tell if its something I will ever be able to use.
Looking forward to playing with the ESP32-P4, if it ever arrives.

[MK14]

EDIT: Sorry, the AliExpress store, kept on refusing to let me find the item for you.
Here it is on a German version (probably affiliate link, from where I found it), and it could disappear (the link) at any time.
https://heise.digidip.net/visit?url=https://de.aliexpress.com/item/1005007259059322.html

There have been English links in the past.
Probably best to get the link directly from the Expressif main product website, when they have stock (again) and are happy to advertise it.

Looking forward to playing with the ESP32-P4, if it ever arrives.

I think they have been distributing (selling), a very small number, of initial (maybe not fully working) development units.

N.B. Make sure you only buy it from the real Expressif store at the original prices, not some reseller at perhaps three times the launch price.

As a development kit, from Expressif (Via their AliExpress outlet, stock is patchy, I've seen it in-stock, at least once) for around £45, with a 7 inch display and other stuff, in very limited quantities.

The Expressif AliExpress store front:
https://www.aliexpress.com/store/1100220184

There is a (hopefully shortly to be released, they are waiting for the chips to arrive, the first or early units, are already done, if I understand the situation, correctly) Olimex, €10 .. €15 (estimated price, by Olimex) version of the ESP32-P4 development board, which is a bit like a PICO.

https://www.hackster.io/news/olimex-teases-a-low-cost-dual-core-risc-v-dev-board-built-around-the-espressif-esp32-p4-84333cbefeaf

Olimex Blog about it:
https://olimex.wordpress.com/2024/07/25/esp32-p4-dual-core-risc-v-open-source-hardware-board-is-almost-finished/