LPDDR2 32bit chip on 16 bit bus

[glenenglish]

I dont know a whole lot about DDR control protocol bitty gritties.  I know enough to make most work
However, I have a project that needs 16 bit LPDDR2 interface
and I have several trays of 32bit LPDDR2 in stock.
Those that know LPDDR2 will know they're the same footprint, just a few extra pins used for the upper two banks (extra DQs, extra DQSs, extra mask bits)
However first thought that comes to mind if just ignoring the upper two lanes.....  is when the ram does a burst read, its going to burst the readout from the memory across all four lanes, and thus the burst lengths when the controller requires say 64 bytes which might be 16 clocks (ddr) over 2 lanes, the chip will expect to output 8 clocks over 4 lanes.  so that isnt going to work.

Anyone been down this before I read up the nitty- gritty detail ?
AFAIKT - from reading the datsheets,  the answer is no, and I should buy 16 bit RAMs instead.
-glen

[asmi]

I'm going to to side with datasheet on that one. I've read some article about using DDR3 x16 module in x8 mode, which seemed possible, but I don't know much beyond that.

[glenenglish]

Some reading later.....

The burst length "BL"  is in words, then the chip and the controller won't care, and that will work.

just got to tie the bit mask for the high lanes low.   things to think about- unaligned accesses, wrapping bursts over boundaries.

what  else... DQ pattern calibration output is ram to controller, so that's fine.

anyone got any informed comment ? Aol it will cost is a bit of power, all those extra cells being refreshed/ charged.

Interestingly the 32 bit and 16 bit parts have same operating currents LOL. probably same chips but 32bit are the binned parts .