Hey guys, I'm working on a simple project using the DE0-nano and Quartus II and I'm very confused about how the clocks work or how to set them up.
This started because I was working on something(I'll post the code below) and it would run correctly for about .1 second and then all the outputs would just either hold their value or go to zero. I couldn't find any reason for this and the time that it would run was seemingly random(IE some times it would be .2 seconds other times is would be .09 seconds or somewhere in between). So this made me think that it wasn't the program getting stuck somewhere.
I then looked at the warnings and I saw a lot of them in reference to clocks but I didn't really understand what they meant. Unfortunately I'm very confused so my question is kind vague. So if someone could give me and idea of what I'm doing wrong or a place where I could learn about this more thoroughly that would be great.
So I don't really understand how the clocks work in this. When I started I thought you didn't really have to put much thought into the clock and I found a megafunction called altclkcntr which seemed to make a global clock. So I thought this was great.
Here are the warnings I'm getting.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived. Clock: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: clock1|pll1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: in_clock was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: clock1|pll1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock in_clock is never referenced in any input or output delay assignment.
The main module, although I doubt that this one is very important. The only thing that would probably matter is the part in the beginning where I connect the clock.
module LED_Matrix_Solid_Color(
input wire in_clock, reset,
output wire clk_out, latch_out, OE_out,
output wire[5:0] color_out, // Color will hold all the color data in the form [r1,r2,g1,g2,b1,b2] where x1 is the top row and x2 is the bottom row.
output wire[2:0] row_out // This specifies the row but two are choosen at once. so 1-8, 2-9, 3-10, ect
);
wire clock;
clock_mod clock1( .CLOCK_50MHZ(in_clock), .CLOCK_1MHZ(clock) );
// Symbolic state definitions
localparam [2:0]
start = 3'b000,
clock_data = 3'b001,
latch_clock = 3'b010,
display = 3'b011,
clock_data_wait = 3'b100,
display_clock = 3'b101;
// Internal definitions
reg[2:0] state, state_next;
reg[5:0] color, color_next;
reg latch, latch_next, OE, OE_next, clk, clk_next;
reg[7:0] count, count_next;
reg[2:0] row, row_next;
// FSMD register and data specifications
always @( posedge clock)
begin
if (reset)
begin
state <= start;
color <= 0;
latch <= 0;
OE <= 1;
count <= 0;
clk <= 0;
row <= 0;
end
else
begin
state <= state_next;
color <= color_next;
latch <= latch_next;
OE <= OE_next;
count <= count_next;
clk <= clk_next; //Needed for the clock to complete one period
row <= row_next;
end
end
// FSMD next state definitions
always @*
begin
// Define default cases
state_next = state;
color_next = color;
latch_next = latch;
OE_next = OE;
count_next = count;
clk_next = clk;
row_next = row;
case (state)
start:
begin
latch_next = 0;
OE_next = 1;
color_next = 6'b001010;
row_next = 0;
state_next = clock_data;
end
clock_data:
begin
if (count < 191)
begin
color_next = 6'b001010;
clk_next = 1;
count_next = count + 1'b1;
state_next = clock_data_wait;
end
else
begin
count_next = 0;
latch_next = 1;
state_next = latch_clock;
end
end
clock_data_wait:
begin
clk_next = 0;
state_next = clock_data;
end
latch_clock:
begin
latch_next = 0;
OE_next = 0;
state_next = display;
end
display:
begin
if (count < 191)
begin
clk_next = 1;
count_next = count + 1'b1;
state_next = display_clock;
end
else
begin
OE_next = 1;
clk_next = 0;
row_next = row + 1'b1;
count_next = 0;
state_next = clock_data;
end
end
display_clock:
begin
clk_next = 0;
state_next = display;
end
default: state_next = start;
endcase
end
// Connect outputs
assign clk_out = clk;
assign row_out = row;
assign color_out = color;
assign latch_out = latch;
assign OE_out = OE;
endmodule
The module that contains the PLL and altclkcntr blocks:
module clock_mod(
input wire CLOCK_50MHZ,
output wire CLOCK_1MHZ
);
// This module will take the 50 MHZ clock as an input
// and output a 1MHZ clock that is also amplified.
wire connect_pll_clock;
pll pll1 ( .inclk0(CLOCK_50MHZ), .c0(connect_pll_clock) );
clock_amp clock_amp1 ( .inclk(connect_pll_clock), .outclk(CLOCK_1MHZ) );
endmodule
I also have an SDC file but I really don't understand it either.
create_clock -period 1000.000 -name clock
derive_pll_clocks
derive_clock_uncertainty
Any info on what I'm doing wrong or where I could learn about this would be great! Thank you for reading.