Question about 82C55 mode 2

[profdc9]

Hello,

I have a question about 82C55 mode 2.  I have attached the following timing diagram from the 82C55 datasheet.  It shows that when RD goes low that IBF is returned to the high state, and when WR goes low OBF is set to the low state.  However, it does not show that the chip select line CS is required to be low and the 82C55 is selected for this happen.

Is the CS line required to be low for the 82C55 so that the WR and RD transition is acknowledged by the 82C55?  If it is not required (WR and RD are monitored even if the CS is high), then do I need to add an external OR gate with CS to ensure that WR and RD only trigger the transition of OBF/IBF when the chip is actually selected?

Thank you,

Dan

[pcprogrammer]

The usage of CS is implied.

In your picture you can see that where the WR line goes low there is a text stating data from CPU to 82C55A, which means there has to be data from the CPU on the bus. Also when the RD line goes low there is a text stating data from 82C55A to CPU, which means the 82C55A is putting data on the bus. This can only happen when the CS line is low. The A0 and A1 lines need to have the right state too.

[RoGeorge]

RD, WR and the data bus are signals going to many chips.  CS is meant to select the chip you want to talk with at a given time.

If CS is not asserted, the data bus and the RD/WR signals will be ignored.

[profdc9]

Ok thanks, but I wanted to double check this is the case.

Dan