The very limited timer provided by RP2040 was the first thing I noticed, at the same time this is mitigated by PIO and PWM as said above.
In addition to those, there are 4 timers dedicated to DMA transfers (with a fractional 16/16 bit divider - still quite limited, as the input clock is fixed to the system clock AFAICS).
I also frankly don't like the data sheet - it's too terse in many areas (specification, clocks etc.) and too verbose (but confused) in others.
That said, on the practical side, in a couple of afternoons last week I put together a simple I/Q modulator on a Pico board to test my always ongoing SDR project.
Core 0 uses tinyusb library to act as an USB sound card - receiving I/Q samples at 48 kS/s (×2 channels) from kiwiradio web or python client on a PC or Raspberry.
The received audio is put in buffers and passed through the HW FIFO to core1 (passing only their address, as the RAM is shared).
Core 1 upsamples the 48 kS/s I and Q to 3.072 MS/s (64×) using the hardware interpolator and then uses them to IQ modulate a precomputed 96 kHz carrier.
The most significant 8 bits are then sent out to the PIO FIFO, and an extra simple R2R DAC + tuned LC converts them to analog.
The pacing of output samples is controlled by the PIO clock - if the incoming and outgoing sample rate drift wrt one another, there might be input buffers thrown away or unmodulated carrier stretches but that has never happened so far.
The spectrum (FFT on a DS1054) looks good enough for my purposes, 2nd and 3rd harmonics are >40 dB below the signal, par for the course with 8 bits.
No need for RTOS, no need for timers or even DMA, extremely simple to use the second core.
HW FIFOs between the cores and between the cores and PIO simplify synchronization and cut on code.
Speed is more than enough* even with code running from XIP flash, thanks also to the HW interpolator.
The cmake based build system is easy to setup, albeit a bit clunky to tailor.
Debugging might be simpler, due to their boneheaded idea of using separate DPs for the cores, but works decently with a J-Link mini EDU and the custom version of OpenOCD.
The SDK is nothing to write home about, but workable and at least the parts I checked did not seem to be extra bloated.
I'm sure I could have done the same on many of the other development boards I have (ST F0-F7, PSoC5, some NXP etc.) but I found that the RP2040 HW and SDK fit like a glove to this task: total written code is about 250 lines + some tinyusb boilerplate (shamelessly copied).
The low price is good too, about 1/3 to 1/2 of Nucleo boards (but they are better, at least for including an onboard debugger).
All in all: a toy, yes, without a clear roadmap or even a vision and one I'd not consider now for a product, but from an hobbyist perspective a fun and cheap toy, with some surprisingly helpful HW for specific tasks.
* I'm overclocking it to 153.6 MHz, to keep a nice ratio between the sample rate and the PIO clock. The 250 lines also include a routine to determine the best integer divisor (no jitter) clock given the maximum overclock frequency, the input and output sample rates and PIO cycles per sample.