BOD and reset generators are notorious for misbehaving at low dV/dt.
I take it these are more speculation than direct observation? Or, say, you might've confirmed a few of these in some systems, but not all of them simultaneously..? (That would be pretty hideous,
but I'm not discounting the possibility..!)
Regarding the scenario -- there should at least, be few things, persistent or destructive, a browned-out core can do. Peripherals aren't doing anything, they're subject to the same malfunctions as any other part; SRAM is going down, and always assumed on boot to be trashed; and EEPROM or Flash, even if accessed appropriately, probably don't have enough charge to finish a write or erase cycle. And even then, they're only likely to corrupt a few points, which could hopefully be detected, but then of course, you do need to implement a validator (CRC or hash, say) to show that the data is as expected at startup. Preferably in a fixed non-writable location; often some Flash is reserved for bootloader use, and protected by fuses that can't be written from software. (Of course, again, who knows what checks might fail during brownout conditions.)
It's also effectively an overclock: at low supply, logic gates don't have enough bandwidth to run at full speed, and that's if the clock generator remains active. So race conditions may corrupt some operations but leave others alone.
Good practice to add a reset generator to the project, just out of habit; they're cheap, small (SOT-23 or less) and better optimized than a digital process trying to fake it with analog circuitry.
RST pins are also notorious for being noise antennas; a bypass cap is a good idea, if you can afford it. Typically 10nF. Cases where that might not be feasible: when the pin is used for serial programming (ATTINY I think for example?).
Tim