Electronics > Microcontrollers

RIP Z80

<< < (18/21) > >>

Howardlong:

--- Quote from: RoGeorge on May 07, 2024, 05:36:16 am ---Less than 10 thousand transistors in total (8500).  No RAM and no EPROM internally, but could generate transparent refresh cycles in case the RAM was DRAM.

--- End quote ---

Transparent in terms of cycles. Not so "transparent" in terms of the glue logic and timing hacks required to satisfy the day's DRAM timings!

All it is is a counter that exposes itself on the address bus on the second half of an M1 cycle.

Of interest was that while the R register is exposed on the lower half of the address bus, the I register is exposed on A8-A15 when \RFSH is asserted. Despite not using DRAM, this undocumented feature was used by Sinclair in their ZX80 and/or ZX81 (I can't remember which one, it might have been both) as part of a crude CRTC: during the horizontal blanking period there was just enough time for a tiny bit of code to run that updated the I register appropriately. The auto-incrementing R register was used as the character count, and the I register as the character row scan count and the address in ROM of the character generator. The intricate details I've forgotten, but this was as a result of reverse engineering it when I was a spotty teenager. I remember calling Zilog to ask them if this was a supported feature, and the answer was "no".

iMo:
Imho, the ice40up5k would be a nice target for a Z80 system (15kB bram and 128kB psram).
20MHz clock should be achievable..

brucehoult:

--- Quote from: iMo on June 02, 2024, 02:12:14 pm ---Imho, the ice40up5k would be a nice target for a Z80 system (15kB bram and 128kB psram).
20MHz clock should be achievable..

--- End quote ---

20 MHz clock with original z80 4-20+ cycles per instruction? That's pretty awful.

There are RISC-V implementations that fit on ice40up5k and do single-cycle (32 bit!) execution at 24 MHz on straight line code, less than 2 CPI on typical branchy/loopy code e.g. 17 DMIPS (0.7/MHz, typical of result bypass but no branch prediction)

z80 does 0.042 DMIPS/MHz when compiled with modern SDCC.

SiliconWizard:

--- Quote from: iMo on June 02, 2024, 02:12:14 pm ---Imho, the ice40up5k would be a nice target for a Z80 system (15kB bram and 128kB psram).
20MHz clock should be achievable..

--- End quote ---

Yeah. I've tried the T80 core on a Lattice ECP5 and timing was achieving over 50MHz. It's probably going to be lower on a iCE40UP. 20MHz should be achievable. I might test that when I get the time, just out of curiosity.
And it's probably possible to do better than the T80 in terms of implementation. It's just that it's a proven design.

Picuino:
Z80 is the microcontroller of my first two computers (a CPM computer and a Spectrum), the first assembly language I learned and the first microprocessor I studied.
It has truly had a long life. This news makes those of my generation a little older.

Navigation

[0] Message Index

[#] Next page

[*] Previous page

There was an error while thanking
Thanking...
Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod