Author Topic: RISC-V assembly language programming tutorial on YouTube  (Read 4168 times)

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RISC-V assembly language programming tutorial on YouTube
« on: December 08, 2018, 01:37:44 pm »
Western Digital (WD) has just posted a 12-part YouTube series in which CTO Martin Fink (!!) presents assembly language programming for RISC-V, using a SiFive HiFive1 with VS Code.

Sadly, they don't seem to be linked to each other.













 
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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #1 on: December 08, 2018, 01:42:25 pm »
Not linked, but there is a playlist
« Last Edit: December 08, 2018, 01:48:07 pm by brucehoult »
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #2 on: December 09, 2018, 01:58:37 am »
Anyone spotted the deliberate (?) error in his assembly language code?

Answer: 729de934392445a122503b40747a83e50b3c4a20
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #3 on: December 09, 2018, 02:23:46 am »
2nd more minor bug: when MTIME wraps around after about 18 hours, while(MTIME < targetTime){} can misbehave, giving a zero delay. Should use while(int(targetTime-MTIME) > 0){}
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #4 on: December 09, 2018, 12:19:50 pm »
Interesting presentation!  I installed the tools and, I must say, I like Visual Studio Code.  It looks a lot like Eclipse with a few more buttons but it works really well.

To add the Debug functionality, you need an account and it seems that something is only temporary because they talk about something happening in about a month.  It costs about $10/month for the Professional version which includes the Unified Debugger and some other features.  Without the debugger option, the IDE is free to use.  Actually, you give up a lot of functionality in the free version.

Well, I couldn't get the debugger to work.  I probably need the board to do that.  The demo doesn't say anything about the board while discussing the debugger.

The HiFive1 board is fairly expensive at around $60 and has no ADCs.  Maybe just use an SPI ADC on a Shield.

Here's where I go off the rails:  Following the demo with 10 lines of C and 3 tiny assembly language files (total 38 instructions), the compiled output is 4,624 bytes of RAM and 53,710 bytes of flash.  To flash an LED!

There seems to be a lot of library code included in the build but since I can't find the linker map file (or how to turn it on), I have no idea how to fix this.  The size doesn't seem to change much when I comment out #include <stdio.h> nor do I know why it was included in the project.

The FE310-G000 chip is FAST - upwards of 320 MHz.
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #5 on: December 09, 2018, 01:19:31 pm »
Interesting presentation!  I installed the tools and, I must say, I like Visual Studio Code.  It looks a lot like Eclipse with a few more buttons but it works really well.

Yeah, I'm allergic to Javascript, but I installed VS Code a while ago and it seems ok. Pretty quick (which Eclipse isn't). I didn't actually realise you could add that kind of embedded programming functionality to it.

Quote
To add the Debug functionality, you need an account and it seems that something is only temporary because they talk about something happening in about a month.  It costs about $10/month for the Professional version which includes the Unified Debugger and some other features.  Without the debugger option, the IDE is free to use.  Actually, you give up a lot of functionality in the free version.

Ugh. I'd pay $10, but not $10/month. I guess I'll stick to using gdb, with or without emacs.

Quote
Well, I couldn't get the debugger to work.  I probably need the board to do that.  The demo doesn't say anything about the board while discussing the debugger.

Sure, he's using the board. You should be able to run the compiled code on qemu, but you're not going to flash a LED that way :-)

Quote
The HiFive1 board is fairly expensive at around $60 and has no ADCs.  Maybe just use an SPI ADC on a Shield.

SiFive didn't have access to analogue IP two years ago then the HiFive1 shipped. Do now.

People have been using:

MCP3008 (SPI) https://www.adafruit.com/product/856
ADS1015 (I2C) https://www.adafruit.com/product/1083

Quote
Here's where I go off the rails:  Following the demo with 10 lines of C and 3 tiny assembly language files (total 38 instructions), the compiled output is 4,624 bytes of RAM and 53,710 bytes of flash.  To flash an LED!

There seems to be a lot of library code included in the build but since I can't find the linker map file (or how to turn it on), I have no idea how to fix this.  The size doesn't seem to change much when I comment out #include <stdio.h> nor do I know why it was included in the project.

There's a tension in supplying IDEs in that beginners just want code they grab from who knows where to work and like to have fully featured libraries, while pros want small code. We definitely default to the former as much as possible. Pros have the knowledge needed to cut the size down if required. And this board has 16 *mega*bytes of flash for the program, so it's not a big issue for beginners.

I haven't tried following these videos yet and don't know exactly what toolchain they're using, but the size seems normal for Newlib. Newlib is really designed for PC use rather than embedded. Even Newlib Nano doesn't help much. We're aware of and working on this...

It doesn't help that ARMs C library gets much smaller size by using a software FP library that doesn't meet IEEE 754 requirements, while ours does.

Using SiFive's freedom-e-sdk I get the following text sizes:

51498 HelloWorld with printf
 2042 program with main() just "return 0"
 6924 Dhrystone using a custom minimal printf https://github.com/sifive/freedom-e-sdk/blob/master/software/dhrystone/dhry_printf.c

Basically, the Newlib printf(), among other things, is pretty bloaty.
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #6 on: December 09, 2018, 04:51:52 pm »
To add the Debug functionality, you need an account and it seems that something is only temporary because they talk about something happening in about a month.  It costs about $10/month for the Professional version which includes the Unified Debugger and some other features.  Without the debugger option, the IDE is free to use.  Actually, you give up a lot of functionality in the free version.

Now I've followed through the presentation actually doing it :-) Yes, using their debugger needs the "pro" version of PlatformIO at $10/month. You do get a free 30 day trial.

I guess the good news is that if you pay that, you can work with 550 or so other boards as well: AVRs, PICs, any number of ARM boards...

It *looks* as though you should be able to use gdb directly. It's given as an option in the debugger menu

 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #7 on: December 09, 2018, 07:58:08 pm »
Thanks for the post Bruce.
Definitely keen to see where all this Risc-V stuff is headed.
Especially that new core/chip designer stuff you are rolling out at SiFive.

As far as VScode goes, PIO is great if you are a beginner not wanting to setup tool-chains etc.
However if your slightly more advanced, using makefiles and GDB within vscode for no cost is super easy! No need to install the great hulk that is PIO.
Just the specific gcc for your MCU (of which you can get pre-built binaries from the SiFive website), and then GDB with the correct script, which you can probably find on the internet for pretty much any board.

Would definitely be interested in looking into some dev boards and MCU's from the E20 series as they come out, especially with integrated ADC's etc...
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #8 on: December 09, 2018, 08:06:59 pm »
Hello,

very interesting subject, but this board HiFive1 is very expensive 59$. I would like to evaluate the "RISC-V" architecture, but HiFive1 board is too expensive for me.
I am vondering if it is possible to evaluate RISC-V architecture using FPGA board and RISC-V Ip-Core? I have few FPGA boards (the biggest one with Artix7 17000 logic cells). I founf link for RISC-V cores:

https://github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs

Has somebody tried RISC-V as IP-core running on FPGA board. Any hints before start?

Kind Regards
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #9 on: December 09, 2018, 10:46:01 pm »
As far as VScode goes, PIO is great if you are a beginner not wanting to setup tool-chains etc.
However if your slightly more advanced, using makefiles and GDB within vscode for no cost is super easy! No need to install the great hulk that is PIO.
Just the specific gcc for your MCU (of which you can get pre-built binaries from the SiFive website), and then GDB with the correct script, which you can probably find on the internet for pretty much any board.

I completely agree. I almost never use an IDE myself, just emacs, gcc, openocd (or avrdude or whatever, as appropriate), gdb. However obviously this tutorial is aimed at beginners, and Western Digital happened to choose VS Code with PIO for it .. so I figured I'd better find out something about it.

Our command-line freedom-e-sdk (which PIO downloads and uses internally) is fairly easy to use itself. For one of the provided projects just type...

Code: [Select]
make software PROGRAM=led_fade
make upload PROGRAM=led_fade

That's it! Now it's running on the board. If you want to do your own program just duplicate one of the example programs, change the name, and you're away.

I personally find it much more understandable to work with standard tools such as shell commands, make, my favourite editor etc than to learn the latest IDE every couple of years.

We do however provide a completely free Eclipse-based IDE "Freedom Studio" that supports GUI debugging, much as PIO does https://sifive.cdn.prismic.io/sifive%2F08af66c3-f408-4ffd-8e92-0428e5b8011a_freedomstudio_manual.v1p3.pdf

Quote
Would definitely be interested in looking into some dev boards and MCU's from the E20 series as they come out, especially with integrated ADC's etc...

SiFive's business model is to enable -- to ENCOURAGE -- *other people* to decide that there will be demand for a chip with a particular core (or cores), memory, peripherals and make it themselves (or Sifive can organise the volume manufacturing, put your logo on the chips etc). With the IP partners added during 2018 this now includes analogue peripherals such as ADCs.

The FE310 and FU540 won't be the last chips SiFive makes, but don't expect to see dozens or hundreds of them, in every possible configuration.
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #10 on: December 09, 2018, 11:01:21 pm »
very interesting subject, but this board HiFive1 is very expensive 59$. I would like to evaluate the "RISC-V" architecture, but HiFive1 board is too expensive for me.

The 3rd-party designed "LoFive" uses the same CPU chip as the HiFive1 and programs are compatible, but it's been available for $25 to $30 at various times. https://store.groupgets.com/products/lofive-risc-v Note that it does require a JTAG programmer, whereas the HiFive1 is programmed using USB, so if you don't already have one you won't see much savings.

You can also buy bare FE310 chips yourself for $25 for 5 on the HiFive1 CrowdSupply page and build your own board. Complete design files for the LoFive are available on github https://github.com/mwelling/lofive

Quote
I am vondering if it is possible to evaluate RISC-V architecture using FPGA board and RISC-V Ip-Core? I have few FPGA boards (the biggest one with Artix7 17000 logic cells). I founf link for RISC-V cores:

https://github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs

Has somebody tried RISC-V as IP-core running on FPGA board. Any hints before start?

Sure! There are literally dozens of cores and cores with peripherals designs for putting into FPGAs from a wide variety of manufacturers.

Probably one of the easiest to get going (and using 100% open-source software) is picorv32/picosoc running on a TinyFPGA BX https://discourse.tinyfpga.com/t/riscv-example-project-on-tinyfpga-bx/451

VexRiscv is also very much worth checking out. It works on a wide range of FPGAs from different vendors, including Artix 7: https://github.com/SpinalHDL/VexRiscv
 
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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #11 on: December 10, 2018, 02:48:21 am »

Here's where I go off the rails:  Following the demo with 10 lines of C and 3 tiny assembly language files (total 38 instructions), the compiled output is 4,624 bytes of RAM and 53,710 bytes of flash.  To flash an LED!

There seems to be a lot of library code included in the build but since I can't find the linker map file (or how to turn it on), I have no idea how to fix this.  The size doesn't seem to change much when I comment out #include <stdio.h> nor do I know why it was included in the project.

There's a tension in supplying IDEs in that beginners just want code they grab from who knows where to work and like to have fully featured libraries, while pros want small code. We definitely default to the former as much as possible. Pros have the knowledge needed to cut the size down if required. And this board has 16 *mega*bytes of flash for the program, so it's not a big issue for beginners.

Basically, the Newlib printf(), among other things, is pretty bloaty.

Yes, newlib is a pig!  But in the demo project, no library function is ever called.  Yes, I imagine some C library functions might be called but it seems unlikely given the code that was written.  I can't see where newlib comes into this project.

I need to look around in the IDE and find the compile/link options.  They have to be there somewhere.  I want to see the assembly output and the link map.

The really good news:  The referenced book, 'RISC V Reader' is less than $20, shipped from Amazon.  The other 2 books are pricey but the author of the videos refers to the 'Reader' as THE book to buy.  So I did...

The interesting part of RISC ISAs is how the hardware handles hazards.  The deeper the pipeline, the more complex it gets.  Throwing away partially executed instructions because a branch was taken but couldn't be predicted because the condition code hadn't been updated from an arithmetic operation that hadn't completed - it gets complicated!

Next question:  How many of the more esoteric op codes does the compiler use?  The problem with building an FPGA version is to ensure you have implemented enough of the instruction set to allow the compiler to generate workable code.  Or, be prepared to rewrite the code generation of the C compiler!

At the moment, the RISC V is in its infancy.  It's been around a while but there is strong competition from ARM and ARM covers quite a broad spectrum of computing.  In the meantime, it's worth knowing how the RISC V works.  If you like knowing that kind of stuff...
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #12 on: December 10, 2018, 03:13:35 am »
but this board HiFive1 is very expensive 59$

expensive? 60 USD are nothing for a board.
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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #13 on: December 10, 2018, 04:21:57 am »
but this board HiFive1 is very expensive 59$

expensive? 60 USD are nothing for a board.

It is essentially a stripped down Arduino, at least in form factor, that runs a lot faster.  The Arduino UNO is $19 at Amazon.  It also has no ADCs which limits its applicability.  What it does have is a LOT of memory.

I'm vacillating, I want to know more about the ISA as a matter of general interest and, truly, $60 isn't a number that concerns me.  But I have to be aware that a) I don't need the board and b) even if I did, it lacks certain features.

So, the book gets here Tuesday and after I skim through it, I'll probably buy the board just to play with it.  Compared to the FPGA boards I have bought, $60 is nothing!

Pipelined processors are interesting and RISC V is definitely approachable at the hardware level (as opposed to just buying an ARM <whatever>).  If I so desire, I can pick up one of the FPGA cores and get right down in the dirt of hardware design.  I like hardware design!

Still vacillating...
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #14 on: December 10, 2018, 05:40:48 am »
It is essentially a stripped down Arduino, at least in form factor, that runs a lot faster.

An Infineon 4500 (Arm core with Cordic) costs something like 45 Euro, so 60 Euro is definitively not too much.


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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #15 on: December 10, 2018, 05:53:34 am »
It also has no ADCs which limits its applicability.  What it does have is a LOT of memory.

my MIPS ATLAS board costs 600 Euro. I got a second-hand one for 120 Euro. It comes with no ADC, DAC, SPI, etc ... just the CPU, 32Mbyte of ram, a PCI bus, two serial line, a couple of timers, LA headers and e-Jtag.

It's not a problem. Simply it's not the kind of target I will ever use to interface a CNC, or a 3D printer. It's not its job, and there are cheaper and better boards for this (Sanguino for example).

I am enjoying my ATLAS board for XINU, and other software stuff that runs more comfortably there. Besides, the e-Jtag makes the experience more comfortable for the debugging point of view.

Still vacillating...

No doubt! And no need to compare a true 32bit RISC processor to ... Arduino1 (at least you should consider Arduino2, or Arduino/Zero ... or Infineon 4500)!

Anyway, if you like RISC-V, go and buy the board  :D
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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #16 on: December 10, 2018, 09:16:53 am »
Anyway, if you like RISC-V, go and buy the board  :D

I decided to buy myself a Christmas present - $75 including tax and shipping.  It'll probably be here next week.
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #17 on: December 10, 2018, 09:58:42 am »
Yes, newlib is a pig!  But in the demo project, no library function is ever called.  Yes, I imagine some C library functions might be called but it seems unlikely given the code that was written.  I can't see where newlib comes into this project.

.platformio/packages/framework-freedom-e-sdk/env/freedom-e300-hifive1/init.c:225:25
Code: [Select]
printf("core freq at %d Hz\n", get_cpu_freq());

On newer versions I've replaced that with a custom itoa() and three puts() which cuts the bloat hugely.

Quote
I need to look around in the IDE and find the compile/link options.  They have to be there somewhere.  I want to see the assembly output and the link map.

PlatformIO isn't supplying all the tools, for example there is no objdump :-(

If you want to poke more deeply you'll be better off using the command-line freedom-e-sdk direct from SiFive. I recommend building it -- it's 25 minutes on a quad core. (but there are precompiled binaries too)

https://github.com/sifive/freedom-e-sdk

Quote
The interesting part of RISC ISAs is how the hardware handles hazards.  The deeper the pipeline, the more complex it gets.  Throwing away partially executed instructions because a branch was taken but couldn't be predicted because the condition code hadn't been updated from an arithmetic operation that hadn't completed - it gets complicated!

No problem in an in-order CPU, which includes everything anyone has shipped so far. Instructions after the branch have been fetched and decoded and their operands fetched, but they don't *execute* until after the branch does .. at which point it is known whether it will branch or not. If the prediction was wrong then execution of already-fetched instructions is squashed and fetch/decode starts again at the correct place.

Quote
Next question:  How many of the more esoteric op codes does the compiler use?  The problem with building an FPGA version is to ensure you have implemented enough of the instruction set to allow the compiler to generate workable code.  Or, be prepared to rewrite the code generation of the C compiler!

All of them!

If you want to build your own CPU in an FPGA then you only need to implement RV32I, which has only and exactly what is needed to compile C code ... but omitting multiply and divide. gcc will happily emit code for this, using library functions for multiply and divide.

The complete RV32I instruction set:

Code: [Select]
Registers r0 ... r31. r0 is always 0, can be used to discard unwanted results (e.g. jal/jalr)
PC is separate. There is no dedicated SP or LR at the hardware level.
All immediate values are signed.

OP rd, rs1, rs2  ; OP = add/sub, slt/sltu (rd=1 if less than, else 0), and/or/xor, sll/srl/sla (shifts)
OPi rd, rs1, 0xNNN ; OP = add, slt/sltu, and/or/xor, sll/srl/sra

lui rd, 0xNNNNN ; load immediate<<12 into rd
auipc rd, 0xNNNNN ; add immediate<<12 to the PC and store in rd

jal rd, 0xNNNNN ; add immediate<<1 to the PC. Store old PC in rd
jalr rd, 0xNNN(rs1) ; add immediate to rs1, clear the low bit, store in the PC. Store old PC in rd

bOP rs1, rs2, 0xNNN ; if rs1 OP rs2 is true add immediate<<1 to PC; OP = eq/ne/lt/ltu/ge/geu

sSZ rs2, 0xNNN(rs1); add immediate to rs1, use as address to store from rs2, SZ = b/h/w
lSZ rd, 0xNNN(rs1); load to rd. SZ = b/bu/h/hu/w (u zero extends, others sign extend)

ecall/ebreak ; no arguments. Call OS or debugger.

There's not a lot of fat there.

Optional: implement only r0 .. r15 and then use -march=rv32e to gcc ("e" for embedded)

Optional: implement multiply/divide -march=rv32im (or em)

Optional: implement atomic operations for SMP -march=rv32a

Optional: implement 16 bit opcodes duplicating the most common 32 bit opcodes for code density comparable to Thumb2 instead of comparable to ARM -march=rv32ic

Optional: implement floating point -march=rv32if or rv32ifd

You can compile any normal C/C++ code and newlib using rv32i or rv32e. The linux kernel and glibc require at least rv32ia (actually I think they require rv64ia at present, but that is being fixed).

Quote
At the moment, the RISC V is in its infancy.  It's been around a while but there is strong competition from ARM and ARM covers quite a broad spectrum of computing.  In the meantime, it's worth knowing how the RISC V works.  If you like knowing that kind of stuff...

Yes, it's early days, but momentum is building.

There is no great *technical* advantage over ARM or MIPS, but also no disadvantage. Compare code size, compare Dhrystone or Coremark or SPEC ... it's a photo finish in most cases. MIPS code is the biggest (and microMIPS doesn't help as much as Thumb or rvc), rv32i is comparable to ARM, rv32ic to Thumb2. In 64 bit, rv64ic is much smaller than anything else (ARM didn't see fit to duplicate Thumb in 64 bit!).

The advantage is that absolutely anyone is free to implement their own CPU (FPGA, ASIC, emulator), call it "RISC-V" if it passes the conformance tests, and use it, sell it, give it away as you please. You are not going to get any nasty lawyers letters.

The advantage over implementing your own instruction set is that someone else already wrote/ported a huge amount of software for you.
« Last Edit: December 10, 2018, 12:38:55 pm by brucehoult »
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #18 on: December 10, 2018, 10:24:57 am »
Yes, newlib is a pig!  But in the demo project, no library function is ever called.  Yes, I imagine some C library functions might be called but it seems unlikely given the code that was written.  I can't see where newlib comes into this project.

.platformio/packages/framework-freedom-e-sdk/env/freedom-e300-hifive1/init.c:225:25
Code: [Select]
printf("core freq at %d Hz\n", get_cpu_freq());

On newer versions I've replaced that with a custom itoa() and three puts() which cuts the bloat hugely.

Yup!  I found the code.  Of course there is also a lot of framework code to initialize the CPU and there is a bunch of space for vectors.  This is typical of modern processors.  In a lot of ways, the vector table feels a lot like ARM7-TDMI.  So does 'start.S'.

I would probably modify the code to just eliminate displaying the CPU frequency.  Maybe I'll try that just to see what  happens.

Quote

PlatformIO isn't supplying all the tools, for example there is no objdump :-(

If you want to poke more deeply you'll be better off using the command-line freedom-e-sdk direct from SiFive. I recommend building it -- it's 25 minutes on a quad core. (but there are precompiled binaries too)

https://github.com/sifive/freedom-e-sdk


I'll try to build the tools next week.  Not a big deal - my main workstation dual boots and it has plenty of horsepower (I7-7700).

I have great expectations of the "RISC-V Reader" book.  I imagine many of my questions will be answered.
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #19 on: December 10, 2018, 10:36:09 am »
Yes, it's early days, but momentum is building.

There is no great *technical* advantage over ARM or MIPS, but also no disadvantage. Compare code size, compare Dhrystone or Coremark or SPEC ... it's a photo finish in most cases. MIPS code is the biggest (and microMIPS doesn't help as much as Thumb or rvc), rv32i is comparable to ARM, rv32ic to Thumb2. In 64 bit, rv64ic is much smaller than anything else (ARM didn't see fit to duplicate Thumb in 64 bit!).

The advantage is that absolutely anyone is free to implement their own CPU (FPGA, ASIC, emulator), call it "RISC-V" if it passes the conformance tests, and use it, sell it, give it away as you please. You are not going to get any nasty lawyers letters.

The advantage over implementing your own instruction set is that someone else already wrote/ported a huge amount of software for you.

I have always been of the opinion that having software to run on a CPU is more important than the CPU itself. 

In the same way, I am looking at microcontrollers as opposed to microcomputers.  I want a bunch of peripherals.  I don't much care about the CPU architecture, if I want to apply the chip to something, it needs peripherals.

I'll be looking at one of the FPGA implementations of the RISC-V to see if I can actually bring up a working CPU.
 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #20 on: December 10, 2018, 03:48:29 pm »
In case anyone is interested in instruction encodings...

 

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #21 on: December 10, 2018, 11:22:31 pm »
oh, it seems there is/will be support for  lauterbach's debuggers  :o
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Online brucehoult

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #22 on: December 11, 2018, 12:42:08 am »
oh, it seems there is/will be support for  lauterbach's debuggers  :o

Already for a year
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Online ehughes

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #23 on: December 11, 2018, 12:56:25 am »
What is the value proposition for this core?     It seems that the value might be for IC vendors to avoid licensing fees from ARM but that is a drop in the bucket compared everything else.     The instruction set doesn't seem all that interesting.    There are a handful of interesting instruction for ARM CM4 (such as SMLAL) and there were interesting features such as bit-banding and simple interrupt handling.   

I am not seeing anything that is particularly useful here?  Or am I missing something?

 

Online brucehoult

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Re: RISC-V assembly language programming tutorial on YouTube
« Reply #24 on: December 11, 2018, 01:44:26 am »
What is the value proposition for this core?

It's not a core, it's an instruction set, like x86 or ARM that can be implemented in many different cores. There are already dozens of different core designs from both commercial and non-commercial sources.

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It seems that the value might be for IC vendors to avoid licensing fees from ARM but that is a drop in the bucket compared everything else.

It's about "Free as in speech, not free as in beer". Yes, you can design your own core or download a free one from github. But that's a lot of work and there are no guarantees or support. Companies such as SiFive, Andes, Syntacore, Esperanto etc are going to want licensing fees just as ARM are (perhaps less, perhaps not).

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The instruction set doesn't seem all that interesting.

It's not intended to be interesting. It's intended to be extremely boring, simple, enabling of both very simple and small implementations and complex high performance implementations, as technically effective as the others, and patent and license-free.

The standard parts of RISC-V very deliberately tread only well worn and established paths that are either provably public-domain in the first place or else covered by expired patents.

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There are a handful of interesting instruction for ARM CM4 (such as SMLAL) and there were interesting features such as bit-banding and simple interrupt handling.   

I am not seeing anything that is particularly useful here?  Or am I missing something?

If you want SMLAL in RISC-V you can add it yourself. Or ask your chip vendor to add it for you. You don't have to persuade the trademark/patent/copyright holder that it's a useful instruction for you and hopefully lots of other users, and wait for them to incorporate it in the next version of their standard and eventually produce chips.

Ok, ARM already did SMLAL in Cortex M4. Cool. But what if you want it in a small microarchitecture such as CM0? You're out of luck. If you want an equivalent to SMLAL in a CM0-sized core such as the SiFive E20 or the Pulpino ZERO RISCY -- no problem, just add it, or have them add it for you.

ARM and Intel have smart people, but will they think of every possible instruction that might make someone's program go 10x or 100x faster? No, they can't. And, worse, if they do add it they're going to add it for everyone -- for your competition as well as for you. Everyone gets any feature that might be useful to anyone .. or else no one gets it. So at the same time you can't get chips with features that you really want, AND you get bloated chips with a lot of features that you don't want.

Radical personalization is the present and future of many industries. Now it's available in CPUs too.
 


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