RISC-V microcontrollers from GigaDevice

[brucehoult]

Just had a short conversation with Sipeed on twitter. They've just received the 2nd batch of 1000 Longan Nano boards, they have over 3000 ordered. The next batch is going to be about three or four weeks away -- which ties in with the delivery date on my order being October 9.

They said once they've caught up on board orders they'll be making the bare chips available too.

[coppice]

A story on the Longan Nano here, although I don't think there's any new info: https://www.cnx-software.com/2019/08/29/longan-nano-gd32v-risc-v-development-board-comes-with-lcd-display-and-enclosure/

And apparently the "Bumblebee" core is actually Andes N22. There's a story here: https://www.cnx-software.com/2019/08/28/andescore-n22-risc-v-core-rv32imac-rv32emac-instruction-sets/

This story doesn't seem to quite match the Gigadevice/Sipeed docs, for example the Sipeed docs say that PMP (Physical Memory Protection .. basically a set of several base&bound registers so you can detect things such as stack overflow or protect machine mode things from user mode code) is not implemented.

They arrived just in time for longan season. 

[mac.6]

A story on the Longan Nano here, although I don't think there's any new info: https://www.cnx-software.com/2019/08/29/longan-nano-gd32v-risc-v-development-board-comes-with-lcd-display-and-enclosure/

And apparently the "Bumblebee" core is actually Andes N22. There's a story here: https://www.cnx-software.com/2019/08/28/andescore-n22-risc-v-core-rv32imac-rv32emac-instruction-sets/

This story doesn't seem to quite match the Gigadevice/Sipeed docs, for example the Sipeed docs say that PMP (Physical Memory Protection .. basically a set of several base&bound registers so you can detect things such as stack overflow or protect machine mode things from user mode code) is not implemented.

I have sources in China that says gigadevice is using Nuclei RISC-V IP and not Andes. Look at https://www.riscv-mcu.com  , FPGA page refers to Nuclei.

[SiliconWizard]

Anyway, it's always nice to see new RISC-V entrants, but I personally don't care much for those small/borderline copycat MCUs (except for the core). Not my thing nor my needs at all. Of course they cover a significant market, just not mine.

I would like to see more of completely original, and a little more powerful RISC-V MCUs (such as the ones SiFive provides, but with more off-the-shelf variants).
The Kendryte initiative was pretty interesting. I got unfortunately disappointed with the lack of documentation and support.

What I would personally be interested in:
- Ultra-low power RISC-V MCUs. There are some that are reasonably low-power now, but still can't compete with ARM-Cortex-based ULP MCUs, and often by far,
- On the other end of the spectrum, beefier (but with still reasonable power consumption) ones, like in the 200-400 MHz range, and a sensible set of peripherals,
- And the absolute ideal: either of the above, but with additional reconfigurable logic blocks (such as a limited number of slices of a typical small FPGA)!

[brucehoult]

A story on the Longan Nano here, although I don't think there's any new info: https://www.cnx-software.com/2019/08/29/longan-nano-gd32v-risc-v-development-board-comes-with-lcd-display-and-enclosure/

And apparently the "Bumblebee" core is actually Andes N22. There's a story here: https://www.cnx-software.com/2019/08/28/andescore-n22-risc-v-core-rv32imac-rv32emac-instruction-sets/

This story doesn't seem to quite match the Gigadevice/Sipeed docs, for example the Sipeed docs say that PMP (Physical Memory Protection .. basically a set of several base&bound registers so you can detect things such as stack overflow or protect machine mode things from user mode code) is not implemented.

I have sources in China that says gigadevice is using Nuclei RISC-V IP and not Andes. Look at https://www.riscv-mcu.com  , FPGA page refers to Nuclei.

It's right there in the datasheet P14:

"Note: The Bumblebee core used for this MCU is jointly developed by Nuclei System Technology
and Taiwanese Andes Technology, and Nuclei System Technology provides authorization and
technical support services.At present, Nuclei System Technology can license the mass-proven N200
series of ultra-low-power commercial processor cores, as well as research a variety of high
performance embedded processor series, and provide customers with customized services."

http://dl.sipeed.com/LONGAN/Nano/DOC/Bumblebee%20core%20intro_en.pdf

[ale500]

I ordered a couple of longan nano board from aliexpress as soon as I saw that they were available. Let's see when they show up...
Regarding the sw, the longan ide installer seems to include platformio, the compiler (so no need to install it extra... ) I already have vs code installed... I just wonder what is lightweight about this vs code...

[ralphrmartin]

Note - although this works on PlatformIO - it doesn't work on a Mac. You'll need Windows.

I ordered my Longan nano withe little LCD for a fiver. It took a while to find out how to drive the LCD, I found this helped:

https://github.com/Kevin-Sangeelee/gd32v_test

[hansd]

A new toy  It never stops.

https://www.seeedstudio.com/SeeedStudio-GD32-RISC-V-Dev-Board-p-4302.html

[GromBeestje]

Oooh! new toys. But I've got to get my "Sipeed Longan Nano" running yet. I can connect to it using JLinkExe, but I haven't managed to get OpenOCD connecting to it.

[hansd]

Which probe are you using with OpenOCD? It works with JLink.

[GromBeestje]

I have an J-Link EDU Mini, and it works with the Seggers JLinkExe tool. At least I've tested connecting, halting, resetting and dumping the flash.

The problem with OpenOCD is probably that I need to find out what configuration file I need. I'm using a git build from the official repository. I've been able to connect, and it reports it recognised 1 hart, but it doesn't reset/halt. And once I got the core working, I also need to figure out the flash.

[trailp]

hi folks

I received a few Lonan-Nano devices a few weeks ago.
I am using Linux, a text editor, Makefile and the installed DFU bootloader

The example code and firmware driver code is quite well laid out and
seems to have an examples for all the peripherals and a most of the
capabilites of the peripherals.  The SDK seems to be Eclipse based
but that is not my cup of tea. 

One thing that caught me out was that you need a modified 'dfu-util'
program to suppoet this chip (at least for Linux).  See this fork
  https://github.com/riscv-mcu/gd32-dfu-utils

I did a pin-toggle speed test and with some unravelling of the example
code 27 MHz can be done in a while loop with the default 108 MHz system
clock.  (Might be possible to do 54 MHz but my inline assembly is not
doing it yet - should be just one line if it is possible)
ADC, DAC, USART, DMA, timer - so fae everything seem to work

At the moment I am having issues getting printf working properly.  After
testing and some thought, I feel the problem is likely to be that I an idiot.

cheers
phil

[ale500]

I got my boards a few days ago. I did not order a specific programmer because I though with the JLink   I could connect. My HW Version is 9.3 (I have the EDU version) and I updated to the latest software (6.56). When I try to connect via Jlink commander, I get a "this J-Link does not support RISCV over JTAG" and it outputs the following through the console:

Code: [Select]

TotalIRLen = 10, IRPrint = 0x0021
JTAG chain detection found 2 devices:
 #0 Id: 0x1000563D, IRLen: 05, RV32
 #1 Id: 0x790007A3, IRLen: 05, Unknown device
Debug architecture:
  RISC-V debug: 0.13
  AddrBits: 7
  DataBits: 32
  IdleClks: 7
Memory access:
  Via system bus: No
  Via ProgBuf: Yes (2 ProgBuf entries)
DataBuf: 4 entries
  autoexec[0] implemented: Yes
Detected: RV32 core
CSR access via abs. commands: No
ConfigTargetSettings() start
ConfigTargetSettings() end
TotalIRLen = 10, IRPrint = 0x0021
JTAG chain detection found 2 devices:
 #0 Id: 0x1000563D, IRLen: 05, RV32
 #1 Id: 0x790007A3, IRLen: 05, Unknown device
Cannot connect to target.

It offers though two other variants SWD and cJTAG, via SWD says:

Code: [Select]

Device "GD32VF103CBT6" selected.


Connecting to target via SWD
ConfigTargetSettings() start
ConfigTargetSettings() end
ConfigTargetSettings() start
ConfigTargetSettings() end
ConfigTargetSettings() start
ConfigTargetSettings() end
ConfigTargetSettings() start
ConfigTargetSettings() end
Cannot connect to target.
J-Link>

Assuming the SWD is the same as in the ARM variant, SWDIO (pin 7 of the JLInk connector) should be connected to JTMS (on the target side) and SWCLK (pin 9) should be connected to (TCK on the target side).

cJTAG says:

Code: [Select]

Selected interface (cJTAG) is not supported by the connected probe.
@: GromBeestje

How did you get it to connect ?

[mac.6]

Debug subsystem is not the "standard" sifive implementation, you I guess you need to use software provided by GD.

[hansd]

You need J-Link HW version 10+ unfortunately. I have the EDU 10.1 and use Segger Embedded Studio with good results.

[westfw]

"this J-Link does not support RISCV over JTAG"You need J-Link HW version 10+ unfortunately.

What?  Why?  I thought JTAG was JTAG, and it was only a matter of software whether you could program a given device?

[ataradov]

What?  Why?  I thought JTAG was JTAG, and it was only a matter of software whether you could program a given device?

I don't konw about this specific case, but Segger really likes to hard-code device IDs into their firmware on limited versions of the hardware (like EDU, SAM-ICE).

[iMo]

Platformio lists the compatible programmers: https://docs.platformio.org/en/latest/boards/gd32v/sipeed-longan-nano.html#uploading

[hansd]

Have a look at https://riscv.org/specifications/debug-specification/
I tried GNU MCU Eclipse plugins and they didn't work all the time. The Segger setup works and is free and fast (except the edu) for non commercial use. The best is it works all the time. Downloading code can also be done via the GD32 DFU tool. I am sure over time there will be more support.

[GeorgeOfTheJungle]

A new toy  It never stops.

https://www.seeedstudio.com/SeeedStudio-GD32-RISC-V-Dev-Board-p-4302.html

He who dies with the most toys wins.

https://m5stack.com/collections/m5-core/products/stickv

[wnorcott]

Hello friends.  I have the Microsoft VSCode and Platformio installed and running on Manjaro Linux (an Arch-based distro) and it runs fine and I can upload programs to the Longan Nano. I bought one from Amazon Prime and is has the 4x2 pin JTAG header pins populated on the board.  Do the ones direct from seeed studio have these pins soldered on?  The product photo just shows unpopulated solder pads.

If anyone is interested I took notes on how to set up the tool stack on Manjaro, it all works.  Next to try is debugging with an Altera USB Blaster clone.

[brucehoult]

A new toy  It never stops.

https://www.seeedstudio.com/SeeedStudio-GD32-RISC-V-Dev-Board-p-4302.html

He who dies with the most toys wins.

https://m5stack.com/collections/m5-core/products/stickv

That's why I've ordered both the new SparkFun RISC-V boards ... and their ESP32 board just to make the order up to enough to get free shipping...

[andersm]

"this J-Link does not support RISCV over JTAG"You need J-Link HW version 10+ unfortunately.

What?  Why?  I thought JTAG was JTAG, and it was only a matter of software whether you could program a given device?

Two options come to mind: The J-Link dongles are supposed to contain some smarts, which needs device-specific support. IIRC the MCU in the revision 10 is significantly more capable than in the previous version, so it's possible they just ran out of space. The more sinister possibility is forcing a wave of hardware upgrades ahead of the Next Big Thing.

[coppice]

"this J-Link does not support RISCV over JTAG"You need J-Link HW version 10+ unfortunately.

What?  Why?  I thought JTAG was JTAG, and it was only a matter of software whether you could program a given device?

Two options come to mind: The J-Link dongles are supposed to contain some smarts, which needs device-specific support. IIRC the MCU in the revision 10 is significantly more capable than in the previous version, so it's possible they just ran out of space. The more sinister possibility is forcing a wave of hardware upgrades ahead of the Next Big Thing.

J-Link is a rather deceptive name. It implies a single product when it was actually been a succession of products, several of which have obsoleted the previous ones for many users.

[ale500]

The list of compatible devices list the altera usb blaster, something I also have. I'll try with that and report back. If only this Platformio wouldn't what to install itself every time I run it...