S08FL bus clock speed selection

[Circlotron]

MCU has external 10MHz oscillator module.
ICSC1 is #%10000000  external reference clock selected.
ICSC2 is #%00110000  clock source divided by 1.
If I BSET then BCLR the port pin goes high for 1uS. I was expecting 0.5uS seeing it takes 5 cycles.

What have I done wrong?
Chapter 8.3 of attached databook.

Edit - corrected pulse  duration figures.

[DavidAlfa]

It seems a single CPU cycle takes 2 clocks? (T1,T2,T3,T4)

[Circlotron]

2 clocks? On the PA version of that family of micros a cpu cycle takes 1 clock cycle. With a 4 meg external oscillator BSET then BCLR takes 1.25uS. Seen it with my own eyes. I would have thought there would have been some sort of consistency across the family. One thing is for sure, the naming consistency of the registers is an absolute train wreck. What page of the manual is that you posted?

[DavidAlfa]

Oops my bad, I searched HC08 instead HCS08 core!
No idea then...

[Circlotron]

Okay, problem solved. Use the code

Code: [Select]

LDA    #%00011000
STA    ICS_C1

LDA    #%00110110
STA    ICS_C2Thanks to vincentegomez at the NXP forum.

Among other things, the external clock has to be divided down so the resulting frequency is in the range 31.25 kHz to 39.0625 kHz. Bit 5 of ICS_C2 and bits 5,4,3 of ICS_C1 select a divide ratio.