There has to be a catch somwhere.
According to:
Bits 19:16 – CCBVx [x=3..0]: Compare Channel x Buffer Valid
For a compare channel, the bit is set when a new value is written to the corresponding CCBx register. The bit is
cleared by writing a one to the corresponding location or automatically cleared on an UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is automatically cleared when the CCx register is read.
Clearly it does not.
Double buffering is enabled as evidenced by
TCC0->PERB.reg = 8; working and setting
STATUS.PERBV register to 1. This is further confirmed by CTRLBCLR.LUPD register being 0.
The only clue i could find so far is in this sentence here:
When
double buffering is enabled by writing a one to the Lock Update bit in the Control B Clear register (CTRLBCLR.LUPD)
and the PER and CCx are used for a compare operation, the Buffer Valid bit is set when data has been written to a
buffer register and cleared on an update condition.
Also the way this sentence is worded is hard to read for me so i'll try to break it down:
:IF writing a one to the Lock Update bit in the Control B Clear register (CTRLBCLR.LUPD)
and the PER and CCx are used for a compare operation
:THEN the Buffer Valid bit is set when data has been written to a
buffer register.
But CC stands for capture compare, how would PWM work if PER and CCx aren't used for compare op?
CCB can't be transferred to CC when the timer is not running. There can't be an UPDATE even if the timer is not running. Obviously writing the registers directly works regardless.
Also, what is your period at this time? If the period is not set, then there won't be an UPDATE event. For the NPWM mode UPDATE happens when the COUNT==PER. And if both COUNT and PER == 0, then there won't be an UPDATE event.
PER is set to 8 and at 8MHz that gives me a pretty good waveform.
Also writing to CCB[2] even when running does nothing and i'll get a screenshot of the watch window that will show just how BS this whole situation is.