Searching modern MCU with a (classic) 8bit I/O bus

[mac.6]

On kinetis family it's called FlexBus (see AN4393).

[mubes]

I'd take a look at the IMX-RT stuff from NXP (nee Freescale). Nice M7 CPU, 256K of RAM (if you choose the baby brothers of the range, available in FPGA rather than BGA), decent perhiperals and very flexible memory interfaces...you can run all your code on the new beast and just talk to the old stuff for integration purposes. Your legacy bus is going to be so slow by modern standards that the first thing to check up on datasheet wise is if the external interfaces will slow down enough!

Regards

DAVE

[bingo600]

IMHO  ATMega162 in a 40-pin DIP would be the closest Z80 lookalike (5v compatible,DIP etc...)
But only 16K internal flash for program , and not possible to use external flash for program code.
https://www.microchip.com/wwwproducts/en/atmega162

But I'd prob go for an arduino Mega as westfw suggested , primarily due to the extra pins , and more flash

But if you want to be fast or have > 64KB Memory go for ARM

/Bingo

[andersm]

IMHO  ATMega162 in a 40-pin DIP would be the closest Z80 lookalike (5v compatible,DIP etc...)

The instruction set of Renesas' RL78 series is very close to the Z80, but they do not have an external bus. The do scale from small 1K flash parts all the say up to 512K, and pin counts ranging from 10 to 144.

[thermistor-guy]

Hello, for a project that needs to interface some vintage chips and a bit of SRAM I need a reasonable modern MCU that has an 8bit parallel bus, practically a Z80 on steroids .
Sadly the Z80 successors are not doing very well and I was wondering if there is some device cheap and readily available that has such a bus, of course I can implement some crappy bit-banging re-purposed GPIOs, but  would prefer something that has this bus memory mapped.
Any suggestion is well appreciated.

 Cheers,
 DC1MC

Like one other poster above, I like the 80C51 family and its many variants.

You could look at SiLabs as a source. But there is also Rochester Electronics, which takes over many popular chips after they have reached normal EOL:

https://www.rocelec.com/search?searchType=part&q=80c51

Rochester has DIP40, PLCC44, and VQFP44  Atmel 80C51s in stock.

[PCB.Wiz]

In the end still wating for your best IDE/Compiler/Pin matrix programmer combo for the STM and suggestions about some 3v3 input to positive or negative logic level shifters.

Needing to have Logic shifters sounds like a pain, on a Data BUS interface.
If you do need those, something like SN74LVC8T245, has dual supplies, so generates a proper, fast logic hi on both sides.

An alternative could be a MCU part like STC8F/STC8A series, that's 5V operating, so does not need shifters.
 https://lcsc.com/products/STC_507.html?q=sTC8f

which have an ALE/RDN/WRN pins and MOVX opcodes, supporting 64K Bytes of External Memory Map.
Data says there are 4 speed choices on ALE/BUS  setup/hold of 1/2/4/8 SysClks, so it can go quite slow, but the CPU is faster than a venerable Z80.

[rstofer]

I don't know why you would overlook the Zilog EZ80.  It runs at 50 MHz and can address a ton of external memory.  I bought one of the boards and built a daughter card for a Compact Flash and a couple of Serial<->USB ports.  I now have a 50 MHz CP/M machine and it really rips.

https://zilog.com/index.php?option=com_product&task=product&businessLine=1&id=77&parent_id=77&Itemid=57

I used EZ80-F91 which is Ethernet capable.  I didn't implement networking.

Development Kit (with Miniboard)
https://zilog.com/index.php?option=com_product&task=dev_tool_detail&DevToolKit=eZ80F910200KITG

The module itself is $45

https://www.mouser.com/ProductDetail/ZiLOG/EZ80F915005MODG?qs=sGAEpiMZZMs64UhKbFbscbRWLT2XOcn84MaByIK211E%3d

Datasheet for module:

https://www.mouser.com/datasheet/2/450/ps0236-24729.pdf

The development kit is $100

https://www.mouser.com/ProductDetail/ZiLOG/EZ80F910200KITG?qs=%2fha2pyFadugetcl9SiKrLhDU5wGisctBoZZrphgvt3YG5MdSkwZeqg%3d%3d

Did I mention that this system rips?

[rsjsouza]

I haven't seen it mentioned here, but some of the larger TM4C devices from TI have a peripheral called External Peripheral Interface (EPI) which can be used with 8/16/32-bit SRAM, but I have never used it so I can't comment on its implementation details.
 

[PCB.Wiz]

I don't know why you would overlook the Zilog EZ80. 

Maybe this is the reason ?
3.3V power supply

but to replace an older Z80 system it does have appeal, even with added level translators

[thermistor-guy]

I don't know why you would overlook the Zilog EZ80.  It runs at 50 MHz and can address a ton of external memory.  I bought one of the boards and built a daughter card for a Compact Flash and a couple of Serial<->USB ports.  I now have a 50 MHz CP/M machine and it really rips.
...

Zilog also has an 8051 family, which I wasn't aware of:

https://zilog.com/index.php?option=com_product&task=product&businessLine=1&id=164&parent_id=164&Itemid=16002

[DC1MC]

Hello and thanks for all the valuable contributions, much appreciated.
The project isn't abandoned or dead, I'm just waiting for the dev board that I've selected, it's a  NUCLEO-H743ZI.
Because I want to replace the existing logic boards on some rather old but good DMMs and add a bajillion of new functions, I need a CPU/RAM massively bigger than the original 6800 and friends.

I wanted so much to make a 6800/Z80 to SPI bus emulator with a small FPGA/CPLD, but sadly while I can design it, I don't have enough knowledge to do the development of the HDL code .

If I've had such a device, with a 25-50MHz (Q)SPI  on one side and 5V 6800/Z08 compatible bus on the other (interrupts included), then the <Fruit>Pi devices (or any other Linux dev board) would have been perfect for the job with tons of cool features to be added, like massive logging capacity, LXI network interface, USB/Ethernet/Serial/Bluetooth connectivity, improved algorithms, both for measurement and math ops, functions not available in that specific model (sorting components in given limits, temperature measurement with auto adjusting drift,  real big fat linearization/calibration tables,  alarms, etc.) 

But then I don't have it, is just an idea, so I have to try to do with what is available.

 Cheers,
 DC1MC

[technix]

Just to throw it out here: PIC32MZ DA series. If you went with the internal DRAM version and add in some kind of high capacity external storage (e.g. a microSD card on the SDMMC interface) you get what is effectively a Linux box that has an exposed external bus interface. Now you can just program using the regular Linux tools (device memory can be directly accessed through mmap() on /dev/mem) and access it as if it is yet another node on your network.

[legacy]

PIC32MZ DA series .. Linux

haven't yet checked the datasheet, what about the TLB (MMU)? is it fully supported?

personally, I believe ucOS/2/3 is more appropriate for the embedded stuff than Linux

[iMo]

Just to throw it out here: PIC32MZ DA series. If you went with the internal DRAM version and add in some kind of high capacity external storage (e.g. a microSD card on the SDMMC interface) you get what is effectively a Linux box that has an exposed external bus interface. Now you can just program using the regular Linux tools (device memory can be directly accessed through mmap() on /dev/mem) and access it as if it is yet another node on your network.

Does the MZ DA  support the execution out of the DRAM??

[rstofer]

I wanted so much to make a 6800/Z80 to SPI bus emulator with a small FPGA/CPLD, but sadly while I can design it, I don't have enough knowledge to do the development of the HDL code .

If I've had such a device, with a 25-50MHz (Q)SPI  on one side and 5V 6800/Z08 compatible bus on the other (interrupts included), then the <Fruit>Pi devices (or any other Linux dev board) would have been perfect for the job with tons of cool features to be added, like massive logging capacity, LXI network interface, USB/Ethernet/Serial/Bluetooth connectivity, improved algorithms, both for measurement and math ops, functions not available in that specific model (sorting components in given limits, temperature measurement with auto adjusting drift,  real big fat linearization/calibration tables,  alarms, etc.)

But then I don't have it, is just an idea, so I have to try to do with what is available.

 Cheers,
 DC1MC

It's not that hard!  You need to expose a parallel interface and a couple of registers, a bidirectional status register and a bidirectional data register (which don't need to be actually bidirectional inside the CPLD, they just look that way from the outside) and a simple state machine that recognizes that data has been loaded into the data register, sets a status bit to indicate 'busy' and shifts the data out while simultaneously shifting the incoming bits in to the data register.

There are a lot of examples on OpenCores.  Probably none that are exactly right but they provide a start.

As to SPI itself, FTDI makes a device that does USB -> SPI (among other protocols).  I'm pretty sure there is a Linux driver for the PI.

http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf

They even have a pre-built cable:

http://www.ftdichip.com/Products/Cables/USBMPSSE.htm

[technix]

PIC32MZ DA series .. Linux

haven't yet checked the datasheet, what about the TLB (MMU)? is it fully supported?

personally, I believe ucOS/2/3 is more appropriate for the embedded stuff than Linux

It is that TLB MMU that made the PIC32MZ DA series Linux compatible. Microchip has upstreamed the kernel and u-boot, just grab the code, compile using stock Linux MIPS GCC (not XC32) and enjoy. U-boot and its configuration data goes to the internal Flash, and kernel goes to the external storage device. Since that chip also has Ethernet you can also build u-boot to do PXE.

Just to throw it out here: PIC32MZ DA series. If you went with the internal DRAM version and add in some kind of high capacity external storage (e.g. a microSD card on the SDMMC interface) you get what is effectively a Linux box that has an exposed external bus interface. Now you can just program using the regular Linux tools (device memory can be directly accessed through mmap() on /dev/mem) and access it as if it is yet another node on your network.

Does the MZ DA  support the execution out of the DRAM??

It does. AFAIK PIC32 always allowed executing from RAM as long as the MPU is set up properly, and on this chip it is the MMU that need to be set up correctly. U-boot bootloader will do that for you, if you used that to boot up Linux kernel. Having only 32MB RAM does make it a tight fit though, although if you went with the BGA288 version you can go with your own DDR2 memory chip, up to 128MB.

[technix]

If you really dare, there is a chip, CH367, that gives you a 8-bit I/O bus from a PCI-Express x1 interface. Using this chip you can build a CH367 card for your PC, and a external breakout box that gives you the interfaces you need.

[iMo]

Does the MZ DA  support the execution out of the DRAM??

It does. AFAIK PIC32 always allowed executing from RAM as long as the MPU is set up properly, and on this chip it is the MMU that need to be set up correctly.

Double check that.. Afaik the DRAM in MZDA is intended for buffering the graphics only..

The industry’s only integrated DRAM provides expansive storage for graphics, complex communications, and data logging applications.

[technix]

Does the MZ DA  support the execution out of the DRAM??

It does. AFAIK PIC32 always allowed executing from RAM as long as the MPU is set up properly, and on this chip it is the MMU that need to be set up correctly.

Double check that.. Afaik the DRAM in MZDA is intended for buffering the graphics only..

The industry’s only integrated DRAM provides expansive storage for graphics, complex communications, and data logging applications.

Page 51 of the datasheet: there is an MMU on the chip. You just turn on code execution in the MMU and you get DDR code execution.

If you still feel dubious, I might trying to request some samples of PIC32MZ2064DAH176, just so I can build a board with the sole intention of running Linux on it.

[DC1MC]

If you really dare, there is a chip, CH367, that gives you a 8-bit I/O bus from a PCI-Express x1 interface. Using this chip you can build a CH367 card for your PC, and a external breakout box that gives you the interfaces you need.

Well, I've searched for it and found it, I've even triggered a google warning that I may be a robot  , the chip looks really nice and the Aliexpress board is moderatly priced, it emulates nicely an ISA bus.

If I really get some old 8-bit ISA card that I need to use, this will be my first choice, it's nice that it exists.

Too bad it has only a few bits of address, it would have been a step in the right direction for me.

 Thanks for the suggestion,
 DC1MC

 Cheers,
 DC1MC

[DC1MC]

I wanted so much to make a 6800/Z80 to SPI bus emulator with a small FPGA/CPLD, but sadly while I can design it, I don't have enough knowledge to do the development of the HDL code .

If I've had such a device, with a 25-50MHz (Q)SPI  on one side and 5V 6800/Z08 compatible bus on the other (interrupts included), then the <Fruit>Pi devices (or any other Linux dev board) would have been perfect for the job with tons of cool features to be added, like massive logging capacity, LXI network interface, USB/Ethernet/Serial/Bluetooth connectivity, improved algorithms, both for measurement and math ops, functions not available in that specific model (sorting components in given limits, temperature measurement with auto adjusting drift,  real big fat linearization/calibration tables,  alarms, etc.)

But then I don't have it, is just an idea, so I have to try to do with what is available.

 Cheers,
 DC1MC

It's not that hard!  You need to expose a parallel interface and a couple of registers, a bidirectional status register and a bidirectional data register (which don't need to be actually bidirectional inside the CPLD, they just look that way from the outside) and a simple state machine that recognizes that data has been loaded into the data register, sets a status bit to indicate 'busy' and shifts the data out while simultaneously shifting the incoming bits in to the data register.

There are a lot of examples on OpenCores.  Probably none that are exactly right but they provide a start.
    ...snip...

Yes, for an experienced digital designer it's not an issue, more like of a piece of cake project, the stuff from open cores is good for the MCU interface ( all those bus states and IRQ/NMI stuff) and one has to add the logic that you've described and the ser/des for the SPI.

Sadly, I know enough to know that I don't know enough to do it myself  , but if there are any takers, I can assist with the concept, schematic design and of course testing suite with whatever fruitPi or even SPI/USB cable for PC usage.

This thing should be able to emulate whatever 8 bit MCU from the series, besides doing completely new and unexpected things with the poor bus  .

Oh well, I don't think I see it on the Kickstarter very soon, and I can only sponsor very marginally the project, with some German beer and tasty sausage stuff but few euros, if anybody wants to work for these peanuts, let me know  .

   Cheers,
   DC1MC

[rstofer]

BTW, the T80 project at OpenCores is an excellent Z80 core.  I use it for a PacMan game I built a long time back.  I used it about 10 years back to build a general purpose CP/M machine.  Time flies, it may have been farther back.

So, the parallel port interface can be ripped from the T80 core and there are dozens of SPI cores.

Yes, you need to know how state machines work.

Pretend you had 16 console entry switches on an old IBM 1130 computer (a 16 bit machine now implemented in an FPGA) and suppose you had them hooked up to a Microchip MCP23S17 SPI port expander.  You would want to continually scan the switches but to do that you first have to send a command and set up some registers.

http://ibm1130.org/hw/cpu/

Attached is one approach that is known to work.  On the 1130, there is an instruction to read the switches into the accumulator so the interface between the switches and the core is quite simple.  Every other device (card reader, typewriter, keyboard, disk, printer and plotter) use a DMA channel.  The interface is a little more complex (but duplicated 6 times).

See attached CES.txt, a copy of CES.vhd but renamed for the forum.

Yes, you need to understand state machines but I always think of them as the game "Simon Says".  You can only change state when "Simon Says" and some condition is now true.

It isn't that hard!  It was, OTOH, a learning experience.

It's regrettable that between the forum text handling and the vagaries of the Xilinx ISE editor that things don't line up properly.  I did put in the CR/LF chars that are not included with the ISE editor.  You can mess around and make the code look pretty if you have an interest.

[rstofer]

Yes, for an experienced digital designer it's not an issue, more like of a piece of cake project, the stuff from open cores is good for the MCU interface ( all those bus states and IRQ/NMI stuff) and one has to add the logic that you've described and the ser/des for the SPI.

Sadly, I know enough to know that I don't know enough to do it myself  , but if there are any takers, I can assist with the concept, schematic design and of course testing suite with whatever fruitPi or even SPI/USB cable for PC usage.

This thing should be able to emulate whatever 8 bit MCU from the series, besides doing completely new and unexpected things with the poor bus  .

Oh well, I don't think I see it on the Kickstarter very soon, and I can only sponsor very marginally the project, with some German beer and tasty sausage stuff but few euros, if anybody wants to work for these peanuts, let me know  .

   Cheers,
   DC1MC

I was stationed in Mannheim back in '66-'67 and I really like Dinkelacker beer.

If you take a step back, you might find that it's time to learn about FPGAs.  Not only can you implement known blocks such as CPUs and predefined peripherals, there is no reason you can't add just anything you want.

You need to think of the modern FPGA as a virtual dumpster full of logic chips.  You can make anything you want as long as it is digital (and that restriction is going away).  Sure, it takes time and effort to learn the skills but it really isn't that hard.  First you blink an LED and then you implement a CPU - pretty much just like that.  Yes, it's helpful if you have a background in logic design but I don't think it is an absolute requirement.  There are some excellent texts that take you through the design of a modern CPU like a MIPS or ARM.

This book goes from zero to a complete uC - the famous LC-3 project that you can find all over the Internet
"Introduction to Computing Systems" by Patt and Patel  I really like this project.  Among other things the state machine is all laid out, all you have to do is write the code.  If you search Google for 'LC-3' or 'LC-3b' you will find all of the required material to implement the CPU and, better yet, the C compiler and assembler.  A great learning project!

http://highered.mheducation.com/sites/0072467509/student_view0/c_to_lc-3_compiler.html

Here's the more current document for the 'b' version which adds some 8 bit data handling:
http://users.ece.utexas.edu/~patt/09s.360N/handouts/new_byte.pdf

Here are two books (one MIPS and one ARM) that have a ton of VHDL and Verilog code.  In fact, a complete CPU is completely coded:
"Digital Design and Computer Architecture ARM Edition", Harris and Harris
"Digital Design and Computer Architecture 2d Edition", Harris and Harris - MIPS centric

Then there is a very detailed design of the Z80 CPU by the fellow who designed the Rabbit uP and one of the Z80 upgrades.  He uses Excel spreadsheets to lay out all of the instructions and timing.  Very clever!  Code in Verilog

"Microprocessor Design Using Verilog HDL" Dalrymple

If you want to play in the Z80 sandbox, this is the book to buy!  Just hang a Compact Flash to the project and implement CP/M with all 16 drives.  Add whatever peripherals you want.  Although I prefer the Nexys DDR because it has a lot of LEDs and switches, the Artix would be a great board:

https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/
https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/

Either should be able to run a Z80 core at 100 MHz.  Guaranteed 50 MHz.  The Artix has a lot of BlockRAM so system memory isn't much of a problem and the DDR memory can be made to look static using a memory core provided free by Digilent.

And a book on implementing primitive blocks like decoders, muxes, state machines and so on:
"HDL Chip Design" Douglas J Smith.  This books shows alternate methods for implementing the building blocks.  Some methods are better than others.

[technix]

If you really dare, there is a chip, CH367, that gives you a 8-bit I/O bus from a PCI-Express x1 interface. Using this chip you can build a CH367 card for your PC, and a external breakout box that gives you the interfaces you need.

Well, I've searched for it and found it, I've even triggered a google warning that I may be a robot  , the chip looks really nice and the Aliexpress board is moderatly priced, it emulates nicely an ISA bus.

If I really get some old 8-bit ISA card that I need to use, this will be my first choice, it's nice that it exists.

Too bad it has only a few bits of address, it would have been a step in the right direction for me.

 Thanks for the suggestion,
 DC1MC

 Cheers,
 DC1MC

Then check out the bigger CH368, which has a bigger address bus and the option of going with a 32-bit data bus.

[andersm]

Double check that.. Afaik the DRAM in MZDA is intended for buffering the graphics only..

That may be the marketing reason for putting the SDRAM in the same package, but it's just RAM. The DDR2 SDRAM memory region is mapped to the KSEG0/1 areas, so there's no MMU setup needed as long as you stick to kernel mode.