Sharing a 32kHz CMOS oscillator

[Koen]

Hello,

     in a previous topic, I've asked you for help sharing a 26MHz 0.8Vpp clipped sine wave oscillator between multiple square wave inputs and ended up solving it easily like schema #1. Thank you.

     I would now like to share a 32.768kHz 2.8Vpp CMOS oscillator between multiple square wave inputs. These tolerate 1.2Vpp maximum so I placed a resistive divider after the oscillator output to yield 0.8Vpp.

     With only one inverter connected for testing and one 1000pF or 0.1uF or 0.22uF or 1uF DC-Cut capacitor in between, STM32 Low Speed External oscillator does not lock. Without the capacitor, it locks fine. But, without the DC-Cut capacitor, will this one inverter bias the whole net and cause problems for the other inverters later ? Or is the correct DC-Cut capacitor different to the ones tested ? Or is this fundamentally wrong ?

    The inverters are internal to the chips used and I can't disable/bypass them.

Thank you very much,
Koen

[babysitter]

Go for bigger dc-block capacitors, consider to bias each input for itself (maybe a full voltage divider is not necessary, a pull up or pull down might be enough)

[tszaboo]

Why would you DC block a clock signal? What is the point?
Nothing is specified as 1.8V p-p signal, they say 1.8V CMOS or something like that. If you AC couple something, that will not be CMOS.
In fact, my digital electronics teacher said, if anyone places a capacitor in a digital circuit (we were discussing TTL, except bypassing) he will personally make sure that the person never gets a degree.

[Koen]

As I, wrongly maybe, understand it : the DC-Blocking capacitors isolate the DC-Bias of every chip clock input circuitry from the oscillator output.

I didn't study electronics at school. I try to learn reading datasheets and manuals but on this rare occasion, Google isn't helping.

[edavid]

Go for bigger dc-block capacitors, consider to bias each input for itself (maybe a full voltage divider is not necessary, a pull up or pull down might be enough)

He said he tried 1uF, which is only 4 ohms reactance, so that's not it.

OP, if you put it in the external oscillator configuration, it won't have a self biasing resistor.  Try internal oscillator/external crystal mode, if that makes sense.
Or tell us the MCU part number.

[Koen]

Hello,

   I've discovered new datasheets from other manufacturers offering schematics with capacitive dividers which I'll try this weekend.

   I reset the board hardware for a fresh start and only have connected the 2.8V CMOS TCXO output to the 2.8V CMOS input through a 100nF capacitor. This chip, an STM32, has the possibility to disable the internal buffer indeed. It works fine.

   I'll see how far I can go with the two other chips. One has no documentation about using an external oscillator except "it's possible" and I haven't received an answer yet but the question was acknowledged by an engineer so I'll probably wait tuesday for his answer.

   The last asks for 0.35Vpp maximum, 0V minimum, 1.6V maximum and an engineer recommended a resistive divider followed by a blocking capacitor.

Thank you !

[Koen]

Here is a "Falstad schematic" of my current idea. It's yet to be tried as I don't want to ruin the pins of the chips : http://tinyurl.com/falstad-32k-osc-2

Is anything fundamentally wrong ?

Thank you for your help.

[PA0PBZ]

Here is a "Falstad schematic" of my current idea. It's yet to be tried as I don't want to ruin the pins of the chips : http://tinyurl.com/falstad-32k-osc-2

Is anything fundamentally wrong ?

Thank you for your help.

 - Simulate at 32KHz, not 100Hz.
 - Put something resembling the input of the chips at the now open outputs.

[Kalvin]

I do not see any sense to play with the capacitors as the proper way would be to use buffers and buffering. Even if one needs some fancy biasing and amplitude control, the buffered approach would give superior reliability in terms of signal integrity. One should not select the fastest buffer components available on the market as the fast rising/falling pulse edges may cause EMC problems.

[Koen]

STM32 datasheet mentions 5pF input capacitance and +/- 1µA of leakage current. I've also added a resistive divider version. Is the schematic correct ? http://tinyurl.com/falstad-32k-osc-4

Falstad circuit allows up to 25kHz and 100us/div.

Thank you !

[Koen]

Hello Kalvin, could you please explain how a buffer would help in this case ? Honest question as I can't find anything by Google.

The traces from the source to consumers are 4, 10, 12mm long 50ohm strip lines (ground around, below and above), the frequency is low and nothing needs to be synchronized. I don't think there is noise or drive issues. It also works great for the 26MHz oscillator.

Thank you !

[matseng]

Why not just use a buffer/level translator?  Texas Instruments got a handy selector to list the relevant parts for any in/out voltage selection.
http://www.ti.com/logic/docs/translationresults.tsp?sectionId=458&voltageIn=2.5&searchDirection=1&voltageOut=1.2#voltintf

[Kalvin]

You could consider something like drawn in the attachment (sorry poor quality).

Firstly, there is one buffer driving the other buffers so that the 32kHz clock signal driving the buffers will be loaded as little as possible.

Then, you should notice that each of the shared clock nets contain a buffer, thus the nets are essentially isolated from each other. For example, if you place a scope to one of the clock nets, the others will not be affected and the signal quality driving each net will be as good as possible. Also, if there are any reflections in the PCB traces, the reflections are isolated and do not interfere each other. Otherwise you can experience multiple clock edges which will ruin your day. So, you should consider isolation technique as a good thing.

Next you should notice that each output buffer contains a 50 ohm series resistor. This resistor will provide series termination and impedance matching for driving the nominal 50 ohm PCB traces. I would use the series resistors even if the PCB track is short that it necessarily require termination - just in case there is something that needs to be tweaked or measured.

There is an optional receiver buffer (the dashed blob in the middle driving the device A). In your case this is not necessary, but it it drawn there to indicate where the receiver buffer should reside: At the far end of the PCB trace, that is.

Finally, then there are two resistor networks at the far end of the PCB trace next to the devices A and B which can be used to provide fancy biasing and amplitude scaling, unless you are willing to use proper receiver buffer with proper level translation. The resistor tweaks are typically usable up to few megahertz. At higher frequencies one should seriously consider using proper level translators and/or buffers. The impedance of the resistor network should be at least 1kohm ohms in order not to affect the signal amplitude too much as the signal is driven through a 50 ohm resistor.

The scheme presented here scales well up to few megahertz or more. For higher frequencies and long PCB traces one should consider using differential drivers for the PCB clock networks for better signal quality and less EMI interference.

Btw, if I understood the STM32 datasheet correctly the STM32 clock inputs can be driven by an external logic-level clock signal.

[Koen]

Thank you ! Once again, I'm not knowledgeable so don't take this the wrong way but is this a state-of-the-art proposition or is it most definitely required ?

I tried the resistive divider + dcblock capacitor for the 0.35Vpp input and it works. So two out of three chips are clocking.

From press releases, it seems the underlying controller in the last chip could be Atmel SAMD20 but, unless I missed it, its datasheet (16.6.3 and 32.11.2) does not specify electrical specifications for the 32.768kHz clock input pin either. It simply mentions the possibility of using an oscillator instead of a crystal.

[Kalvin]

The suggestion was not the state of the art, just common practice when one wants to make things work without getting into a trouble

One can do a simple variant that can be used when the PCB traces are short and the buffer driver is slow enough so that the reflections do not cause false clock edges (top scribbling, see attachment). Notice that the 50 ohm resistors are placed as close to the driving buffer as possible.

Typically the buffers come in packages of four or six, so there is no real reason not to use a separate buffer for each clock signal shown in the bottom drawing.

Btw, sometimes debugging clock edge problems can be challenging if you do not have proper measurement instruments available. For example, the clock signal edges may look fine on 100MHz oscilloscope screen although you are experiencing mysterious problems. But when looking the same signal with 500MHz oscilloscope and good probes one can see jagged clock edges causing multiple clock transients in fast logic devices. Why not design the clock nets right in the first place.

[Koen]

Isn't #2 a 1:3 fanout buffer ?

Is this what should be done with the 26MHz 0.8Vpp clipped sine wave oscillator too ?

Thank you !

[Kalvin]

Isn't #2 a 1:3 fanout buffer ?

Is this what should be done with the 26MHz 0.8Vpp clipped sine wave oscillator too ?

I would definitely use #2 for the 26MHz clock after the clipped sine wave is first converted to a proper logic level signal in order to feed the input buffer (the common buffer).

[Koen]

Last time, I moved the 3 required 26MHz crystals to one oscillator because all-in-all, it was the same price and the frequency tolerance jumped from 20ppm to 0.5ppm. The oscillator is right next to the chip making use of this improved accuracy and I don't care about the accuracy near the other chips.

This time, the 32k clocks aren't even required. All the chips have internal RTC oscillators which work well enough to track time and save a few other things. Yet, one chip "could" use improved frequency tolerance and I've stumbled upon a cheap 10ppm oscillator. I haven't tested for improvements yet but all-in-all, this clock circuit shouldn't be perfect as long as it is better than say 100ppm.

Now, with this relaxed use of the clocks, is it worth adding buffers ? The 26MHz with DC-cut capacitors works great according to the practical use I have of it and a good quality frequency counter (nicely shared by a third party for this one occasional test). A quick look at Digikey seems to point that buffers are expensive (> 1 USD / 100), massive (> 8WSON, 8TSSOP) and hungry for current (> 2mA, outputs unused). The 32k oscillator will run all the time and consumes 15µA. Overall, the actual consumption is 70µA in standby. Unless I missed the obvious small low-current < 2 USD/100 buffer, the options now would only be to forget about an external 32k oscillator or hope for the best with capacitors.

Another way to put it would be : what will go wrong with capacitors instead of buffers ? Thank you for your answers !

[edavid]

Another way to put it would be : what will go wrong with capacitors instead of buffers ? Thank you for your answers !

Nothing.  If you can get the right voltage levels without buffers, it will work fine.
It just takes a little more thought to get it right.