Electronics > Microcontrollers

Simple FPGA problem - Error when assigning - Verilog

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pigtwo:
Hey guys.  I was just attempting a very simple design for an FPGA(Just a d flip-flop) and I am getting a weird error.

Every time I try to assign something, it tells me that the first thing is unexpected.  I'm sure it something simple, but I just can't seem to see it.

Here's my code:

--- Code: ---
module dflipflop(

input wire clk, data,
output wire out1

    );


wire q1, q2, q3, q4, q5, q6, q7, q8, q9, q10;

assign out1 = q9;

assign q1 = data ~& q2;
assign q2 = !clk;
assign q3 = q1 ~& q2;
assign q4 = q1 ~& q5;
assign q5 = q3 ~& q4;
assign q6 = clk;
assign q7 = q4 ~& q6;
assign q8 = q6 ~& q7;
assign q9 = q7 ~& q10;
assign q10 = q8 ~& q9;


endmodule

--- End code ---
And this is the error I'm getting:

--- Code: ---ERROR:HDLCompilers:26 - "dflipflop.v" line 33 unexpected token: 'data'
ERROR:HDLCompilers:26 - "dflipflop.v" line 35 unexpected token: 'q1'
ERROR:HDLCompilers:26 - "dflipflop.v" line 36 unexpected token: 'q1'
ERROR:HDLCompilers:26 - "dflipflop.v" line 37 unexpected token: 'q3'
ERROR:HDLCompilers:26 - "dflipflop.v" line 39 unexpected token: 'q4'
ERROR:HDLCompilers:26 - "dflipflop.v" line 40 unexpected token: 'q6'
ERROR:HDLCompilers:26 - "dflipflop.v" line 41 unexpected token: 'q7'
ERROR:HDLCompilers:26 - "dflipflop.v" line 42 unexpected token: 'q8'

--- End code ---

Again, I'm sure it's something stupid and obvious, but just can't seem to figure it out.

Thanks!

jmole:
Don't use the word "data" in your code

pigtwo:
I changed it but I'm still getting the same error.

pigtwo:
Ok, I seem to have figured it out.

Apparently it didn't like the '~&' operator.  I misread this off a website and thought it could be used as an NAND.  It seems to only be an unary operator. 

FrankBuss:
Right, but you can use the concatenation operator to implement the NAND. And there is a missing "endmodule". "data" should be no problem. This compiles in Quartus:

--- Code: ---module dflipflop(
input wire clk, data,
output wire out1
);


wire q1, q2, q3, q4, q5, q6, q7, q8, q9, q10;

assign out1 = q9;

assign q1 = ~& {data, q2};
assign q2 = !clk;
assign q3 = ~& {q1, q2};

endmodule

--- End code ---

Of course, it doesn't make sense, because you didn't assign a value to q9. And I would use the edge triggered commands (posedge clk) for implementing a d flip-flop, as you can see at http://en.wikipedia.org/wiki/Verilog

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