EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: legacy on December 19, 2015, 05:25:50 pm
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so xmas is coming, I have a more free time and my hobby(1) gets involved in Symmetric multiprocessing (also known as SMP), which involves a symmetric multiprocessor system hardware and software architecture where two or more identical processors and I'd like to learn something about from a good book as currently I am learning from the linux sources, which is the worst way ever :palm: :palm: :palm:
Feel free to suggest me an idea, suggestion, a book title (or its ISBN) to be filled in the end corner of my wishlist in Santa Claus's letter, hopefully we are still in time :D
thank you
(1) I am dealing with two R12K MIPS4 64 bit, trying to fix a few troubles with linux
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the wiki only provide jurassic references, such as:
- IBM System/360 Model 65 Functional (http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/360/funcChar/A22-6884-3_360-65_funcChar.pdf)
- IBM System/360 Model 67 Functional (http://bitsavers.informatik.uni-stuttgart.de/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf)
Also, I do not understand the detailed difference between multi processors and multi core :-//
Linux and symmetric multiprocessing (http://www.ibm.com/developerworks/library/l-linux-smp/)
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(http://ecx.images-amazon.com/images/I/51Z04V844NL._SX358_BO1,204,203,200_.jpg)
Unix Systems for Modern Architectures: Symmetric Multiprocessing and Caching for Kernel Programmers
1994, by Curt Schimmel
found on amazon, what do you think about the above book ?
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You're going to have to be more specific about what you're looking for. Parallel algorithm design? Implementing SMP primitives? Something else?
Is Parallel Programming Hard, And, If So, What Can You Do About It? (https://www.kernel.org/pub/linux/kernel/people/paulmck/perfbook/perfbook.html) is pretty low-level, The Art of Multiprocessor Programming (http://www.amazon.com/The-Multiprocessor-Programming-Revised-Reprint/dp/0123973376) is more concerned with design and correctness of parallel algorithms.
Also, I do not understand the detailed difference between multi processors and multi core
Multicore is a form of multiprocessing. A multicore processor has multiple cores(!) in the same processor (same die, or same module). This means they usually share L3 and L2 cache, and are more tightly coupled than processors in different sockets.
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Parallel algorithm design? Implementing SMP primitives? Something else?
everything! I do not know anything about SMP, nor hw, nor sw :D
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Multicore is a form of multiprocessing. A multicore processor has multiple cores(!) in the same processor (same die, or same module). This means they usually share L3 and L2 cache, and are more tightly coupled than processors in different sockets.
I am playing with an SMP dual cpu module, 2xR12K processors (MIPS4, 64bit, they are not cores, they are physical chips, two R12K chips), and it uses a completely different method to "pass" commands between CPU0 and CPU1, it's different from e500 quadri-core.
I do not know which kind of atomic instructions are used, e.g. 68000 uses TaS, Test and Set, as read-modify cpu-cycle, I do not know about the cache coherency algorithm. Snoop protocol ? just heard in my computer science course, 4 years ago, what else is used?
and what about coherency algorithms ? I have found the following list in my R12K handbook, while linux implements and uses the 5th, cacheable, coherent, write-back, exclusive on write, sharable (even if … on my board it's not working at all :palm: :palm: :palm: )
/*
* MIPS3_TLB_ATTR (CCA) values - coherency algorithm:
* 0: cacheable, noncoherent, write-through, no write allocate
* 1: cacheable, noncoherent, write-through, write allocate
* 2: uncached
* 3: cacheable, noncoherent, write-back (noncoherent)
* 4: cacheable, coherent, write-back, exclusive (exclusive)
* 5: cacheable, coherent, write-back, exclusive on write (sharable)
* 6: cacheable, coherent, write-back, update on write (update)
* 7: uncached, accelerated (gather STORE operations)
*/
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MIPS uses LL/SC for atomic sections (Load Locked/Store Conditionally). A basic hardware mutex.
algorithm #5 looks like a "MOSI"/"MESI" scheme, this is the most common for quite a while.
I expect this stuff is covered in "See MIPS Run".
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Any decent college-level computer architecture textbook should explain the concepts. Hennessy & Patterson's (http://booksite.elsevier.com/9780123838728/index.php) is one of the best-known.
Like eg. ARM and POWER, MIPS implements atomic operations using load-linked/store-conditional pairs. An easy way to see them in action is to use GCC's built-in atomics and looking at the disassembly.
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and what about the above coherency algorithms ?
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They will also be explained, or at least you will be better able to understand the documentation. Note that the meaning of the field is implementation-defined, and eg. the R10K manual has a substantially different list (the manual also has descriptions of the different caching algorithms.)
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@andersm
which is your practical personal experience with MIPS?
SGI ? Atheros ?
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implementing smp properly on mips platform (http://stackoverflow.com/questions/27099008/implementing-smp-properly-on-a-linux-mips-platform) :-+
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books (https://www.linux-mips.org/wiki/Books#General_computer_architecture)
caches (https://www.linux-mips.org/wiki/Caches)
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Years ago I learned something about SMP from one of Tom Shanley's books: Pentium Pro Processor System Architecture (http://www.amazon.com/Pentium-Processor-System-Architecture-Series/dp/0201479532%3FSubscriptionId%3DAKIAILSHYYTFIVPWUY6Q%26tag%3Dduckduckgo-ffsb-20%26linkCode%3Dxm2%26camp%3D2025%26creative%3D165953%26creativeASIN%3D0201479532). I am not sure if it is really good or not, I just got the information I wanted at the time.
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Maybe read some OpenCL tutorial?