ST 32F417 ADC1 or ADC2 input impedance

[iMo]

To your measurement - an Si diode has got -2mV/K drift of the forward voltage..
Also with stm32 (as it has been discussed a few times here) you would hardly get the ADC noise below 2-3 LSB bits without a 4 layer pcb and a careful routing (plus careful decoupling) with none capacitor at its input..

[peter-h]

Yes, I know the -2mV. The setup was temperature stabilised for hours and the measurements were taken in rapid succession. I have a ~1ppm reference source as well but would not expect it to show anything different on the ADC noise side of things.

The PCB is 4 layer and the 100nF cap goes straight to that. The various "ground" pins are appropriately separated, too. 100nF is an overkill of course; you could never make much use of a 1msps ADC with a 100nF cap across the input I just wanted to see how much noise the ADC had. It's a 10-11 bit device; I can't see getting all 12 even with a buffer right next to the ADC input pin on the CPU.

But then few if any 1msps applications need 12 bits. Looking at the amazingly complex architecture of the ADC subsystem, it is intended for stuff like 3 phase AC inverters for motor control, engine ECUs, etc, and none of that needs anywhere near 12 bits.

[T3sl4co1l]

BTW, are you measuring the source, or the reference, at this point?

It might pay to hook up a ratiometric source, so that Vref factors out.

Tim

[peter-h]

OK; I repeated the test ratiometrically, feeding the input from around 90% (1k1/10k) of Vref (TL431A, 2.5V) and with the 100nF cap across the 10k.

3 - 2.2392V
15 - 2.2392V
28 - 2.2395V
56 - 2.2397V
84 - 2.2398V
112 - 2.2398V
144 - 2.2398V
480 - 2.2399V

I thin repeated it with a 42MHz ADC clock, which is above the 36MHz max spec. At say 56 sample period I got 2.2388V which is quite a bit down, plus there was a 0.0002V variation either side so something is not working right. Remember this is averaging 1000 readings. But at 480 I got a steady value of 2.2401V.

56 - 2.2388V
480 - 2.2401V

The tempco of the ADC gain is also low - with the reading changing from 2.2400 to 2.2397 (56 sample period) as the CPU warms up. Probably of the order of tens of ppm/degC.

[aheid]

Which board did you use for testing?

With the STM32F103 you can get less noise depending on board, but of course the chip is quite different so could be that as well.

[peter-h]

It is my own PCB; not the ST development kit anymore. That board was extremely noisy; there were long tracks all over the place, with clocks etc...

On the original Q on this thread, I can report that the ADC Zin is pretty high. I am feeding ADC2 from a 2x10k 0.01% divider (Zout=5k obviously) and the readings multiplied by 2, and calibrated for the actual Vref, are

15 - 3.2865V
56 - 3.2895V
480 - 3.2901V

The actual voltage on the top of the divider is 3.2940V so the drop is about 0.1% which would suggest a Zin of about 5Mohms on the 56 and the 480 sample period settings and about 2Mohms on the 15 setting. This Zin is presumably dynamic; the effect of charging the capacitors. Plus maybe some leakage. This is as expected but it's interesting to get a handle on it like this.

So to get the error (due to source loading) under 1 LSB you would need a source Zout of about 500 ohms. I don't know how that relates to that ST formula.

But, bear in mind this is really a "10 bit ADC" so 0.1% is in the right ballpark anyway Well, unless you are happy to average the last 1000 readings, which is what I am doing to get these values.