Spartan 3E board

[asmi]

And advising to stay with the last technology, just because it's super-fast, super-amazing, super-wonderfull ...  is just like being too obsessed with what the market needs to promote.

7 series is not the last technology as there are Ultrascale and Ultrascale+, which really is super amazing, but unfortunately it's also amazingly expensive But compared to equivalent chips from 6 series, 7 series is both better and cheaper!

Besides, THE point was the cost of these boards! Since Spartan3 is obsolete, boards come very cheap!

They are cheap because they are crap - the same reason they are obsolete.

[KE5FX]

It is true that flexibility in I/O standards has gotten somewhat worse since Spartan6,

Can you please elaborate on that? The only standard that is missing on 7 series is 2.5 V (sans (B)LVDS), but I can't think of any chip that would require it except DDR1, which itself is long obsolete.

It's not so much a question of missing I/O standards as how many supplies you need to support common standards.  Compare table 1-55 in UG471 (7-series) with table 1-5 in UG381 (S6), for instance.  On 7-series if you want LVCMOS18 input support in a given bank, you need Vcco=1.8V, and likewise for other standards (LVCMOS25, LVCMOS33, etc.)  On Spartan6 you could use lots of different input voltage standards regardless of Vcco.

[hamster_nz]

It is true that flexibility in I/O standards has gotten somewhat worse since Spartan6,

Can you please elaborate on that? The only standard that is missing on 7 series is 2.5 V (sans (B)LVDS), but I can't think of any chip that would require it except DDR1, which itself is long obsolete.

I too have a gut feeling that the earlier Spartan 3E chips had far more flexible I/O pins.

Maybe it is because the more advanced dev boards run I/O banks at just the voltage you don't want to use...

and it is also true that XDC constraints are a tire fire.

Well there is GUI for creating/editing timing constraints, although typing them directly is probably easier for experienced designers.

IMO Hand-editing the XDC file is really the only way to go to ensure you you get what you really want, in a nice clear concise set of statements.  I has also to be said that the syntax is awful compared with the 'primitive' UCF files used in ISE.

However, doesn't everybody just take the vendor's standard XDC with the devboard and uncomment a few lines and change the signal names

[KE5FX]

However, doesn't everybody just take the vendor's standard XDC with the devboard and uncomment a few lines and change the signal names

[asmi]

It's not so much a question of missing I/O standards as how many supplies you need to support common standards.  Compare table 1-55 in UG471 (7-series) with table 1-5 in UG381 (S6), for instance.  On 7-series if you want LVCMOS18 input support in a given bank, you need Vcco=1.8V, and likewise for other standards (LVCMOS25, LVCMOS33, etc.)  On Spartan6 you could use lots of different input voltage standards regardless of Vcco.

Well it's a trade-off between performance, on-chip power consumption and flexibility. And honestly that requirement makes a lot of sense to me as odds are whatever peripheral you're talking to is going to require that voltage for its' IO buffers.

[asmi]

Maybe it is because the more advanced dev boards run I/O banks at just the voltage you don't want to use...

Well designed devboards allow you to set I/O voltage to what you need. And this is how I design my own devboards too. For example here is my most recent board:

Note zero ohm resistor and an empty footprint for another one at the lower right side of the board (as it is on a photo). By moving this resistor I can set IO voltage of one of connectors to 1.8 or 3.3 V. Second one is fixed at 1.8V as I'm using 1.8V QSPI flash chip for bitstream here.

IMO Hand-editing the XDC file is really the only way to go to ensure you you get what you really want, in a nice clear concise set of statements.  I has also to be said that the syntax is awful compared with the 'primitive' UCF files used in ISE.

I actually found GUI for timing constraints pretty solid once you get used to it. Same goes for pin assignments - though I rarely use it as in most cases layout and routing drives pin assignments. I only use it after I completed board layout so that I can run P&R to make sure I didn't do anything stupid like using incorrect pin for clocks, or some other special functions (like aligning buses to IO byte groups in case I will need to use IO FIFOs in design).

However, doesn't everybody just take the vendor's standard XDC with the devboard and uncomment a few lines and change the signal names

Well since I design boards myself I've become quite adept at writing pin constraints Though I mostly write such file only once for a given board, and then just copy-paste it across designs. Same goes for MIG project file and DDR3 pin assignment files - but this gets a little more complicated in case I have several identical boards but fitted with different pin-compatible FPGAs. I also extensively use exporting diagram to tcl script function to save time for subsequent designs.

[avogadro]

Go for an Artix board.

Which board do you recommend that is 100ish euros?

[KE5FX]

Go for an Artix board.

Which board do you recommend that is 100ish euros?

What are your goals and your current level of FPGA experience?  I like the ZTex boards a great deal because they are fully documented, but I'm not sure if any are available at that price point.  For learning, something like the Arty board from Digilent might be better.  I'm not sure Digilent has EU distribution, though, or if it's prohibitively expensive over there.

[avogadro]

Well have started learning vhdl couple of months ago and I was planning on doing the LC3B project but before I get into that I would like to get more comfortable with vhdl and play around with leds, switches, 7-segment displays etc...

I looked on the webs and yeah artys are almost double the price here in europe... I could get that ztex for 150?