Spartan 6 current consumption

[poorchava]

I'm designing a board with Spartan 6 FPGA (SC6SLX9-TQG144 to be exact) and I'm trying to figure out what parameters my power supply has to have, but all I got from internet search is "impossible to say without knowing the actual design". I understand that exact current consumption is hard to tell without the design, but I'm simply looking for a safe value.

My design is not hobby, but not a high volume either (a dozen or so pcbs for test rack), so I don't worry about oversizingr the power supply. FPGA is powered from 1V2 (Vccint) and 3V3 (everything else). I just need a general guideline like "1V2@100mA and 3V3@200mA is already excessive" or "more than 500mA on both rails is necessary" or something like that.

Any of you guys has any experience with that?

[mikeselectricstuff]

Xilinx have a software tool to estimate power draw of a design based on clock rates etc.

[marshallh]

Design for 1-2A on 1v2 if possible, or whatever core voltage it uses. The IO current draw is something you can easily estimate on your own.

[EEVblog]

You have to use the power consumption estimation tool, and then do that for say 80% gates used at the frequency you intend to use at to get an estimate of a max figure.
Yes, it's totally dependent upon the design and clock rate(s).
They do have a base static consumption, but that doesn't tell you anything.
Beware of traps like startup current, which can be much higher than your design consumption. So your PSU design has to be able to handle the brief power-on current too.
I don't recall if this is the case for the Spartan 6 though, but worth investigating.
All the manufacturers have very extensive apps documents on this.

[mikeselectricstuff]

A quick way to get an "it won't be worse than this.." figure is to look at what regulators they use on devboards for that part.  These may be over-specced, for worst-case usage, however it will be a pretty safe bet.

[Hardcorefs]

Xilinx have a software tool to estimate power draw of a design based on clock rates etc.

And it FAILS VERY badly..........

[Hardcorefs]

I'm designing a board with Spartan 6 FPGA (SC6SLX9-TQG144 to be exact) and I'm trying to figure out what parameters my power supply has to have, but all I got from internet search is "impossible to say without knowing the actual design". I understand that exact current consumption is hard to tell without the design, but I'm simply looking for a safe value.

My design is not hobby, but not a high volume either (a dozen or so pcbs for test rack), so I don't worry about oversizingr the power supply. FPGA is powered from 1V2 (Vccint) and 3V3 (everything else). I just need a general guideline like "1V2@100mA and 3V3@200mA is already excessive" or "more than 500mA on both rails is necessary" or something like that.

Any of you guys has any experience with that?

It depends on:

1. Your FPGA logic speed.
2. How BADLY it is routed.
3. Utilisation.


Design  it for 5A and you will not go far wrong......,  yes yes I know... "my design will never use 5A" , go CAREFULLY READ the xilinx configuration notes for the beast.
It's not how much 'your' design consumes, nor the figure the Xilinx tools give you, but rather the startup requirements when the beast first comes up and has to get its house in order BEFORE you even get a bit file near it......

[poorchava]

wouldn't a large cap help? I mean at 1.2V or 3.3V a large capacitor can be quite small. Like for example EEVFK0J332Q from Panasonic? Or 3 1000uF's in parallel?

I have some (erm.... a few reels) switching regulator chips capable of 1.5A at hand.

[Hardcorefs]

wouldn't a large cap help? I mean at 1.2V or 3.3V a large capacitor can be quite small. Like for example EEVFK0J332Q from Panasonic? Or 3 1000uF's in parallel?

I have some (erm.... a few reels) switching regulator chips capable of 1.5A at hand.

Nope... long term it would KILL the PSU...  the issue is transients as the logic is switching, so .... lots of  100nf-1uf ceramics right on top of the FPGA vias.., with main Ceramics in the + (I.E center of the FPGA breakout)



This beast just runs.... and runs... and runs  even at 70Deg C. ambient......

no shitty electrolytes to dry up  you see......

[poorchava]

My chip is not BGA, but QFP. And yes, tons of ceramic caps will be there as well as low esr tantalum caps.

[flynnjs]

Take say the Digilent Atlys board and it uses 2-3A parts on both rails.

[nctnico]

I second Mikes suggestion to look at the eval boards for a safe assumption. You can always include check points for measuring the current in your prototype and downsize regulators if necessary / possible.

[lorth]

Xilinx have a software tool to estimate power draw of a design based on clock rates etc.

And it FAILS VERY badly..........

Indeed. I don't know right now how the tool in Xilinx works, but 2-3 years ago you could either put some probabilities of switching the different lines, what blocks where you using...(Very wizard like...) or to do a simulation of your code in a simulator, post layout pref., (ModelSim...) create a .vcd file, and then use that in power estimation software and then multiply by a factor. And then of courser, the power-up current...

I guess you need to use Xilinx... but lots of this problems (power-up current and power consumption) if size (and some times speed) is not a big issue is to go with Actel (Microsemi, ok ok) Igloos or ProAsics3...

[poorchava]

Size is not an issue - having a hardware DSP block or something else capable of ~350MHz binary counter is.

I'm pretty much settled with spartan 6.