Yes, when /CE and /OE are pulled low by the unpowered circuit, the RAM's outputs assert. Probably at address 0 for the same reason. /WR should be pulled low too but check the datasheet for precedence (I think it's still read?). If you'd stored nonzero data at that location, the active pins will be backfeeding the bus, probably putting a few volts into the circuit via ESD diodes.
This is confusing. If /CE, /OE, and /WR are all low, the databus will be Hi-Z, and data will be overwritten.
Conversely, when /CE is high, /OE and /WR are don't cares.
74HC125 and the like, with /OE's driven from inverted VCC (note the inverter needs to be powered by VBAT), will deassert the signal and the pullups to VBAT take over.
If you use 74HC32 as I mentioned, you don't need pullups.
Ah, write-dominant after all, got it. Which will hold the chip active of course, but won't do more than that. Doesn't seem to be any reason then that it would "drain rapidly"...
Or, HC32 needs an inverter still, but since it's just CE needing the treatment, a 74HC2G02 will do it all in one chip.
The Schmitt trigger is a nice touch; I don't know that it's really necessary, so what if it chatters a bit? -- Well, depends if /WR is read as asserted during that time, doesn't it. Which is a concern for whatever type of gate here, so, that probably helps but isn't a guarantee, hm.
Really what should be used, is something to detect failing power, before it crosses any logic threshold -- then you can guarantee no data loss during power cycles. An active-high reset generator / voltage detector IC would be perfect here.
Tim