Author Topic: SRAM ce line  (Read 3206 times)

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Offline T3sl4co1l

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Re: SRAM ce line
« Reply #25 on: July 21, 2021, 08:38:29 pm »
Yes, when /CE and /OE are pulled low by the unpowered circuit, the RAM's outputs assert.  Probably at address 0 for the same reason.  /WR should be pulled low too but check the datasheet for precedence (I think it's still read?).  If you'd stored nonzero data at that location, the active pins will be backfeeding the bus, probably putting a few volts into the circuit via ESD diodes.
This is confusing.  If /CE, /OE, and /WR are all low, the databus will be Hi-Z, and data will be overwritten.

Conversely, when /CE is high, /OE and /WR are don't cares.

Quote
74HC125 and the like, with /OE's driven from inverted VCC (note the inverter needs to be powered by VBAT), will deassert the signal and the pullups to VBAT take over.
If you use 74HC32 as I mentioned, you don't need pullups.

Ah, write-dominant after all, got it.  Which will hold the chip active of course, but won't do more than that.  Doesn't seem to be any reason then that it would "drain rapidly"...

Or, HC32 needs an inverter still, but since it's just CE needing the treatment, a 74HC2G02 will do it all in one chip.

The Schmitt trigger is a nice touch; I don't know that it's really necessary, so what if it chatters a bit? -- Well, depends if /WR is read as asserted during that time, doesn't it.  Which is a concern for whatever type of gate here, so, that probably helps but isn't a guarantee, hm.

Really what should be used, is something to detect failing power, before it crosses any logic threshold -- then you can guarantee no data loss during power cycles.  An active-high reset generator / voltage detector IC would be perfect here.

Tim
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Offline Benta

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Re: SRAM ce line
« Reply #26 on: July 21, 2021, 09:04:29 pm »
Really what should be used, is something to detect failing power, before it crosses any logic threshold -- then you can guarantee no data loss during power cycles.  An active-high reset generator / voltage detector IC would be perfect here.

Tim

I'm totally with you here, the main power supervisor should ideally be tied in to this. But as we have no idea what it looks like, it's pure guesswork.
All the rest is a workaround, and my suggested circuit was meant as such (read: quick fix).
 

Offline T3sl4co1l

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Re: SRAM ce line
« Reply #27 on: July 21, 2021, 10:36:27 pm »
No I mean that as a quick fix too -- supervisors are as jellybean as transistors, handy for many things besides reset generation as such!  Although that's pretty much the application here, so it's a natural fit. :)

Tim
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Offline hedleyTopic starter

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Re: SRAM ce line
« Reply #28 on: July 22, 2021, 09:03:21 am »
Many thanks to all for response . See summary attached and we have ordered the parts and will try out Benta suggested " quick fix .
 

Offline hedleyTopic starter

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Re: SRAM ce line
« Reply #29 on: July 22, 2021, 03:47:19 pm »
The joys of pandemic - just have  been advised that earliest shipping date for 74LVC1G17QW5 is 23 June 2022 . GRRRRRRR
 

Offline edavid

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Re: SRAM ce line
« Reply #30 on: July 22, 2021, 04:03:07 pm »
The joys of pandemic - just have  been advised that earliest shipping date for 74LVC1G17QW5 is 23 June 2022 . GRRRRRRR

Thousands in stock at DigiKey, Mouser, Newark  :-//

https://www.findchips.com/search/74LVC1G17QW5
 

Offline hedleyTopic starter

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Re: SRAM ce line
« Reply #31 on: July 22, 2021, 04:06:48 pm »
Tks will look - I noticed that I started the exercise on 2017 and gave up - see forums topic “ Battery power “ . I know remember that this is where the 2N7000 was suggest as well as the DS1250 NV ram which now runs at $ 94 per chip on mouser and is a dip so would need a converter PCB and rework of all boards installed in the field .
 

Offline oPossum

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Re: SRAM ce line
« Reply #32 on: July 22, 2021, 04:16:13 pm »
 

Offline hedleyTopic starter

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Re: SRAM ce line
« Reply #33 on: July 22, 2021, 04:45:01 pm »
After a day of measurements key major issue is the voltage drop across the 10k pull-up resistors on the CE lines . If I lift the processor pins then there is only .46 volt drop so CE line high value is within spec . With processor pins connected then volt drop is 4.16Volts resulting in the CE lines being under 1Volt. To make things more difficult the processor datasheet does not have output and input pin impedance values . If I measure between lifted processor pin and ground on a non powered board the resistance is 330k ohms .m
 

Offline Benta

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Re: SRAM ce line
« Reply #34 on: July 22, 2021, 05:03:48 pm »
The joys of pandemic - just have  been advised that earliest shipping date for 74LVC1G17QW5 is 23 June 2022 . GRRRRRRR

You may not need it, I put it in there as a safety measure (important with 5k units in the field). You should be able to test the circuit using only the 1G66 parts. The VDD/Battery diodes should be Schottky types of course.
An alternative solution is using two 74LVC1G14 in series, they may be easier to source.

 

Offline hedleyTopic starter

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Re: SRAM ce line
« Reply #35 on: July 22, 2021, 05:10:29 pm »
Thanks , we’re in the jungle here in South Africa , and normally purchase through RS - Components . I’ll give mouser a try as if this works we have to mod about 1000 boards , so will buy a reel and make a small add on , board that we can do on our in house prototyping p & p machine .
 

Offline hedleyTopic starter

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Re: SRAM ce line
« Reply #36 on: July 23, 2021, 05:55:41 pm »
Where I started in 2017 which worked on sim . I’ll wait for parts and build as per benta suggestion
 

Offline SiliconWizard

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Re: SRAM ce line
« Reply #37 on: July 23, 2021, 06:17:25 pm »
The joys of pandemic - just have  been advised that earliest shipping date for 74LVC1G17QW5 is 23 June 2022 . GRRRRRRR

Yeah. OTOH, it's never been easier to get junk food delivered at your door within 30 minutes. Maybe that says something about our priorities? ;D
 

Offline hedleyTopic starter

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Re: SRAM ce line
« Reply #38 on: July 24, 2021, 08:47:30 am »
lT spice sim which also works , so ill give the fet based solution one more try . The 4k7 in place of 10k pullup will help meet SRAM VCC to CE/ line criteria for data retention , and importantly I did not have the n channel fet drain resistor to ground in original circuit so it basically never turned off to isolate the processor .
 

Offline T3sl4co1l

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Re: SRAM ce line
« Reply #39 on: July 24, 2021, 09:50:57 am »
It's a fine solution at DC.  But try it with a 100 ohm, 5ns rise PULSE at nCE.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


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