Author Topic: SRAM ce line  (Read 1561 times)

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Offline hedley

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SRAM ce line
« on: July 20, 2021, 08:07:22 pm »
I have some old boards using intel 80188uC with 2 x sram chips . I want to retain data in the sram when VCC fails. I connected a wired or diode pair - one to vcc and 1 to a nimh battery pack . When battery pack is powering the system the other side of the diode goes only to the power pin of the SRAMs and a pull-up resistor to both CE lines.

The battery runs down rapidly - it appears as if when the CPU has no power the output CE lines ( lcs & ucs) are draining the battery , I suspect through protection diodes internal to the chip . I cut the traces on the PCB to verify this , which does seem to be the case .

Request for help - please can someone send a diagram of how I could perhaps insert a mosfet “ in line “ on the two CE lines so that they effectively go “ open circuit “ when battery is powering the memory and then close when VCC is restored.

Any help much appreciated .

hedley.davidson@gmail.com
 

Online SiliconWizard

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Re: SRAM ce line
« Reply #1 on: July 20, 2021, 08:33:38 pm »
can you show us a small schematic of your mod?
 

Online Benta

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Re: SRAM ce line
« Reply #2 on: July 20, 2021, 11:33:20 pm »
A possibility could be a 74HCT1G66 in series with the CE line powered from the OR'ed battery/VCC line. Connect the control input to VCC.

A better idea would be using FRAM or NVRAM instead of SRAM. Would also eliminate the battery.

« Last Edit: July 20, 2021, 11:35:11 pm by Benta »
 

Offline David Hess

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Re: SRAM ce line
« Reply #3 on: July 21, 2021, 01:36:01 am »
The way battery backup is normally done is to include some extra discrete logic between the processor bus and memory to control -CE which itself is powered by the same backup supply so when power to the processor is removed, no extra load is presented to the battery.
 

Offline hedley

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Re: SRAM ce line
« Reply #4 on: July 21, 2021, 09:07:50 am »
Firstly excuse poor drawing - its an age thing  :(. I was needing advice on how to insert the 2N7000 in the circled areas. The thinking is that when there is VCC the FET will be on thereby providing a low impedance patch for the 2 * CE lines.
Then when VCC is removed the fet will turn off thereby preventing the battery VBAT draining through the CE line on the CPU , as it seems to be sinking current through the esd protection diodes internal to the chip as the pin is pulled high by the 10K resistors
therefore forward biasing the high side esd diode . FRAM is not an option as we have over 1000 of these boards in the field for the last 25 years and they use a K6XX4008CIF-GB70 OR BS 62LV4006SIP55 OR BS 62LV4007SC-70 all of which are 32 pin form factor so I have been unable to find the same foorprint FRAM or NVram + they are very expensive so I was hoping to Frankenstein a solution
 

Offline hedley

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Re: SRAM ce line
« Reply #5 on: July 21, 2021, 10:52:03 am »
I TRIED TO ADD A MORE READABLE DIAGRAM - see attached .

The yellow circles are where the switching FET's would be needed . I guess as the 2n7000 is enhancement mode ,  it would also need a pull down resistor on the gate ? . The gate would be connected to the VCC line so that when there is vcc the fet would be on with a Rdson on 5 ohms and an ID of 200ma continuous so may do the job . Th Vgs is 800mv so dont see a problem turning it on . The key questions are :

1. Would this work
2. Has anyone else seen an unpowered processor drain batteries through the I/O pin esd diodes.
3. Which way around must the fet be installed - I think with Drain facing the pull-up resistor and the Source connected to processor pin ?
 

Offline oPossum

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Re: SRAM ce line
« Reply #6 on: July 21, 2021, 02:28:32 pm »
This is the easy way: https://datasheets.maximintegrated.com/en/ds/DS1312.pdf
Unfortunately a rather expensive chip.

A CD4066B (to switch CE, WE, RD) and a power good circuit may be a workable solution.
 

Offline hedley

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Re: SRAM ce line
« Reply #7 on: July 21, 2021, 02:44:41 pm »
Thanks for response but as mentioned before the pin out and footprint are different which would require a new layout and production run plus field replacement and as it is a 25 year old system the client wants a cost effective “ band aid fix “ . Some years ago I saw a circuit using a fet to do exactly this , but can’t remember - duh . If I measure between processor CE pin and VSS with a meter on un unpowered board it is 6k4 and almost the same between the CE pin and VCC.

The requirement appears simple - supply battery power and hold CE/ high to retain data . This works fine BUT due to the CE/  line on the processor chip the battery drains in about 20 hours . The battery is a nimh 4.8V , 2400mAh pack .
 

Online edavid

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Re: SRAM ce line
« Reply #8 on: July 21, 2021, 02:56:31 pm »
2N7000s are not suitable for 5V logic since the VGS is too high.  You would need logic level FETs.

I don't think a 4066 or even an HC4066 is a good idea because of RC delays.  HC4066 should be OK.

However, these are logic signals, so there's no need for analog switches.  A 74HC32 + inverter (or TL7705/some other supervisor IC) would probably work well.

How are you going to prevent the CPU from scribbling on the SRAM during power down?  Do you have control of the firmware?

« Last Edit: July 21, 2021, 06:47:27 pm by edavid »
 

Offline hedley

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Re: SRAM ce line
« Reply #9 on: July 21, 2021, 03:04:02 pm »
I did order some analogue switches as per a pervious post . I thought the Vgs was 800mV ? . I will look at your suggestions and yes we wrote all the firmware back in the day . The EPROMs we used were end of life many years ago so overall a bit of a challenge which I’m sure all on the forums are used to . I aged a lot due to two words in our industry ( EOL and MOQ ) , especially being in low volume industrial electronics where systems have to last 10 years at quotation time.
 

Offline CJay

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Re: SRAM ce line
« Reply #10 on: July 21, 2021, 03:17:38 pm »
How is it drawing enough current through a 10K resistor to deplete a 2.4AH battery in 20 hours?

My head and my calculator say that's less than half a mA so I don't think it can be draining it through the /CE line, could it be as simple as an incorrect resistor?

have you measures the current drawn through the cut track?

What am I missing?
 
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Offline hedley

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Re: SRAM ce line
« Reply #11 on: July 21, 2021, 03:33:05 pm »
Yes I use a Rigol DP832 bench supply to provide the - VBAT and therefore can monitor and plot the current drawn . I was also confused so cut the tracks at the two CE  outputs of the processor LCS and UCS on pin 100 and pin 92. As soon as the tracks are cut then current to power the ram goes down to uAmps .

Regarding the other question of scribbling the ram contents I am proceeding based on pulling CE line high soonest , which then ignores the read and write lines .
 

Online SiliconWizard

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Re: SRAM ce line
« Reply #12 on: July 21, 2021, 03:41:12 pm »
Can you not just "isolate" the CE lines with diodes? So adding a diode between the processor's signal and the CE line of the RAM chip? This way you have a OR function between the microprocessor and your backup battery.
 

Offline hedley

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Re: SRAM ce line
« Reply #13 on: July 21, 2021, 03:42:08 pm »
I agree that something odd is going on . Ohms law would suggest that a 4.8 volt battery through a 10k would take a long time to discharge. If I measure with a scope the one side of the 10K is at 4.8v as expected and the other side which is the CE line pull-up is at 1.02v . Which would suggest 378uA is being drawn . I’m based in SAafrica so have left office and will start afresh in the morning . Thanks again for sanity check , it normally ends up being a simple error as outlined in the book “ the dog barks when the phone rings “
 

Offline hedley

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Re: SRAM ce line
« Reply #14 on: July 21, 2021, 03:47:36 pm »
I did try that as a first step but the vf of the diode .6 volts caused issues under normal operation . That then led me to look for mosfets with a low rds in the region of max 5 ohms . And then I fell down the rabbit hole and was hoping someone had had issues with a non powered processor chip providing paths to voltage rails where I suspect the current is flowing , do to cutting the tracks at the processor , resulting in significant reduction in current drawn .
 

Offline CJay

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Re: SRAM ce line
« Reply #15 on: July 21, 2021, 03:48:53 pm »
Ahh, so it must be enabling something else which is drawing all the current through the diode on the VCC line.

Is VCC to the SRAM chips isolated from the rest of the board or is it perhaps somehow still connected to some other components too?

 
 

Offline hedley

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Re: SRAM ce line
« Reply #16 on: July 21, 2021, 04:02:32 pm »
We use Cadence Allegro for PCB design . On PCB Editor , When I select the net eg LCS the only devices connected are the SRAM pin 20 the processor pin 92 and the pull-up resistor . As far as power is concerned the VBAT net is connected to the pull-up resistor and the 2 x SRAM chips and 1 x RTC . This makes me think that under battery power all other chips on the board and discretes have no power . I will confirm with measurements as there are things like an old ALTERA flex chip with custom VHDL code and these gobble power .
 

Online SiliconWizard

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Re: SRAM ce line
« Reply #17 on: July 21, 2021, 04:13:04 pm »
I did try that as a first step but the vf of the diode .6 volts caused issues under normal operation .

Ah, I see. You could have tried a Schottky diode, but unfortunately, those tend to leak (in reverse) a lot more. So in the end, you probably wouldn't gain anything much.
 

Online Benta

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Re: SRAM ce line
« Reply #18 on: July 21, 2021, 06:25:36 pm »
I don't think a 4066 or even an HC4066 is a good idea because of RC delays.

What RC delays? passing CE through an analog switch is significantly faster than through a logic gate.
Please explain your thinking.
 

Online T3sl4co1l

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Re: SRAM ce line
« Reply #19 on: July 21, 2021, 06:49:54 pm »
Yes, when /CE and /OE are pulled low by the unpowered circuit, the RAM's outputs assert.  Probably at address 0 for the same reason.  /WR should be pulled low too but check the datasheet for precedence (I think it's still read?).  If you'd stored nonzero data at that location, the active pins will be backfeeding the bus, probably putting a few volts into the circuit via ESD diodes.

MOSFETs won't do here as they have massive capacitance (~30pF), and as mentioned the threshold voltage should be lower to deal with TTL level logic.

An analog switch is okay, given that its resistance is low enough -- with only the RAM's control pins after it, a CD4066 is probably enough, but I'd be more comfortable with a 74HC4066 or better.

Any logic gate that disconnects its output when unpowered, will also work.  A plain buffer function will do, and then it can be powered by VCC, and the pullup resistors to VBAT take over when off.  74LVC family is a good example, though it's not really suitable for 5V (it can be used there, but it's tight, and better suited to 3.3V operation).  I'm not sure if there's a 5V family that does that?

Transmission gates can also be used.  74HC125 and the like, with /OE's driven from inverted VCC (note the inverter needs to be powered by VBAT), will deassert the signal and the pullups to VBAT take over.

The HC4066 is probably the simplest, not needing an inverter; complete logic solutions I think require two chips (e.g., 3 NAND + 3 NOT), or some manner of discrete glue logic, which tends to cost speed or current draw.  The pullups are kind of a compromise, that fortunately don't cost VBAT current because of when they're used.

Tim
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Bringing a project to life?  Send me a message!
 
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Online edavid

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Re: SRAM ce line
« Reply #20 on: July 21, 2021, 06:52:25 pm »
I don't think a 4066 or even an HC4066 is a good idea because of RC delays.

What RC delays? passing CE through an analog switch is significantly faster than through a logic gate.
Please explain your thinking.

Whoops, you're right, at least for an HC4066 or better.

 

Online edavid

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Re: SRAM ce line
« Reply #21 on: July 21, 2021, 07:02:36 pm »
Yes, when /CE and /OE are pulled low by the unpowered circuit, the RAM's outputs assert.  Probably at address 0 for the same reason.  /WR should be pulled low too but check the datasheet for precedence (I think it's still read?).  If you'd stored nonzero data at that location, the active pins will be backfeeding the bus, probably putting a few volts into the circuit via ESD diodes.
This is confusing.  If /CE, /OE, and /WR are all low, the databus will be Hi-Z, and data will be overwritten.

Conversely, when /CE is high, /OE and /WR are don't cares.

Quote
74HC125 and the like, with /OE's driven from inverted VCC (note the inverter needs to be powered by VBAT), will deassert the signal and the pullups to VBAT take over.
If you use 74HC32 as I mentioned, you don't need pullups.

 

Offline hedley

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Re: SRAM ce line
« Reply #22 on: July 21, 2021, 07:05:02 pm »
Thanks for reply and a lot of food for thought . I will go through each suggestion and ensure I understand in depth and then build up on veroboard and test . Expected delivery of some of the components is in 8 days .
 

Offline hedley

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Re: SRAM ce line
« Reply #23 on: July 21, 2021, 07:17:32 pm »
section of sram datasheet showing why my prime objective if to hold CE high.
 

Online Benta

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Re: SRAM ce line
« Reply #24 on: July 21, 2021, 07:52:20 pm »
Here's a suggestion.
If you have more than one CE, you only need  to duplicate U2 and R1.

« Last Edit: July 21, 2021, 07:55:37 pm by Benta »
 
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