Yes, when /CE and /OE are pulled low by the unpowered circuit, the RAM's outputs assert. Probably at address 0 for the same reason. /WR should be pulled low too but check the datasheet for precedence (I think it's still read?). If you'd stored nonzero data at that location, the active pins will be backfeeding the bus, probably putting a few volts into the circuit via ESD diodes.
MOSFETs won't do here as they have massive capacitance (~30pF), and as mentioned the threshold voltage should be lower to deal with TTL level logic.
An analog switch is okay, given that its resistance is low enough -- with only the RAM's control pins after it, a CD4066 is probably enough, but I'd be more comfortable with a 74HC4066 or better.
Any logic gate that disconnects its output when unpowered, will also work. A plain buffer function will do, and then it can be powered by VCC, and the pullup resistors to VBAT take over when off. 74LVC family is a good example, though it's not really suitable for 5V (it can be used there, but it's tight, and better suited to 3.3V operation). I'm not sure if there's a 5V family that does that?
Transmission gates can also be used. 74HC125 and the like, with /OE's driven from inverted VCC (note the inverter needs to be powered by VBAT), will deassert the signal and the pullups to VBAT take over.
The HC4066 is probably the simplest, not needing an inverter; complete logic solutions I think require two chips (e.g., 3 NAND + 3 NOT), or some manner of discrete glue logic, which tends to cost speed or current draw. The pullups are kind of a compromise, that fortunately don't cost VBAT current because of when they're used.
Tim