What's the SRAM input capacitance? What is the µC bus output resistance? What rise time are you aiming for? This will tell you if you need additional series resistance to keep things nice and quiet.
For example, if the µC has Ro = 20Ω, the inputs on the SRAM are 8pF, and you have a 3.3V high level,
Vth = 3.3/2 = 3.3*(1-exp(-t/RC))
=> t/RC = -ln(1-1/2)
=> RC = t/0.69
Targeting for example a 2ns transition time (low to threshold, or high to threshold),
RC = 2.9nΩF
With C = 8pF, you get R = 362Ω. You have Ro = 20Ω, so you'd need to add ~340Ω.
If Ro = 200Ω, add 160Ω.
This is just ballpark, and it's not super critical, so if you have say 100Ω resistors somewhere else, that's probably fine too.
Then stick a low-capacitance probe on the input pins and measure the 0-1.65V rise times to verify, and inspect for overshoot, ground bounce, ringing, or any other crap that doesn't belong. Putting a 10pF probe on an 8pF pin probably is going to hide problems and you're better off going "by the numbers" and trusting those more than what you see on the scope as the rise times will drop significantly with an additional 10pF. But if you see problems with a 10pF passive probe you know you have a must-fix issue.
A lot of modern logic has 3-5pF input capacitances, and modern µC's have the characteristics of modern logic (I've found 74LVC is often a good approximation). Note that modern logic often has a maximum rise time to prevent metastability. Make sure to go over the SRAM electrical specifications and make sure you understand them, how they matter or impact your design, and how to verify each one of them.
This is in the conceptual category of "circuit correctness". Layout is secondary, especially with tiny boards.
A weaker drive is a good idea if an option, and will effectively increase the output resistance. But you still need to do the math.