EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: peter-h on May 20, 2022, 04:05:10 pm
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I don't see any way to do this but perhaps someone might know of some cunning trick.
The chip does have some curious features like the ADC can run continuously and interrupt when the input voltage is outside a window.
What I would like to do is set up a timer to trigger a DMA read of an SPI peripheral, at 125kHz (SPI clock can be up to 5.5MHz on the said device), to a constant memory address. That is definitely possible.
But I would also like to interrupt, or detect in some way which doesn't involve the CPU while looking for it, if the byte received is not 0xFF. Most of the bytes are 0xFF and this signifies "got no data".
The background to this is here
https://www.eevblog.com/forum/projects/anyone-using-the-u-blox-neo-m9n-gps/ (https://www.eevblog.com/forum/projects/anyone-using-the-u-blox-neo-m9n-gps/)
and I have got it running in software, polling the SPI.
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<hack>
Set up an EXTI interrupt on SPI MISO, to interrupt on falling edges.
In the ISR, ensure the SPI transfer is complete, then check and act upon the most recently received data, which you now know contains at least one zero.
Won't work if SPI MISO doesn't stay high all the time, ie. if it goes low when CS is not asserted (use a pull-up), or if it's driven low during the interval between CS going low and the first active clock edge on SCK.
</hack>
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That's very clever - thanks :)
Yes one would to gate MISO with CS so if CS=1 MISO=1.
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I am wondering if one could direct the received SPI data to some fixed address which happens to be a peripheral which interrupts if it sees non-FF, perhaps as a side effect. Maybe a capture register on some timer.
It is fairly obvious this can be arranged with some value (e.g. a value which starts a timer whose compare register is set to 1 so it interrupts immediately) but not so obvious doing it with a non-FF.
For detecting equality to FF, there may well be a timer mode where loading a byte of FF would trigger a compare match and thus an interrupt? Most of the timers are 16 or 32 bit compare types so one would need to preload the other half with FF.
A truly horrid hack would be to use the ADC window interrupt feature, with the ADC input suitably tied to some voltage, and rigged so that any value less than FF creates the interrupting condition.
And there may be a clue: looking for non-FF, one is really looking for any value smaller than FF. That might be a way to use a timer compare reg.
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Another hack idea: IIRC the USART peripheral has some address decode logic. Maybe DMA from the SPI input, into a USART TX, which loop-backs back to RX, which can then use the USART facilities. Would be a hack of the century if it works.
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Hmmm thanks I will look into that one also :)
I wonder if one can also use a USART which doesn't come out on any pin (because you had no pins left).
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Yes one would to gate MISO with CS so if CS=1 MISO=1.
If you're using a timer to trigger a DMA transfer, does that actually allow for control of CS?
Some STM32 devices have a very limited hardware NSS feature, which I've never found useful. I always end up controlling CS in software - in which case you may as well have a timer interrupt which asserts CS, performs the SPI transfer, negates CS and then checks the value of the returned data before exiting.
This does have a performance impact, of course, but it's much more flexible and maintainable than a hardware hack.
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Actually yes you are absolutely right; /CS cannot be done using the chip alone (NSS) unless there are no other SPI slaves connected, and even then you have no control over the two CS timing periods.