We've discovered an errata condition in an ADC where if there is a high-frequency runt pulse on the MCO clock that feeds its' main clock input, it craps out forever until a full power cycle. Now, I've been trying to find a way to start the MCO (fed from HSE input) with a nice rising edge and a full 1/8MHz cycle without any runt pulses. The only option that I see revolved around using a timer's input capture to generate an interrupt on a HSE/32 rising edge, and turn on the MCO output.
Alternatively, just use a busy-wait loop on the input capture flag and "sync" the executing code to the HSE/32, and enable MCO at a convenient location. So far, nothing seems to work due to execution, or some other kind of jitter. Best I could do is about 43ns jitter, or 6-7 cycles at 160MHz. I've tried some bare minimum code so that there's no DMA fighting for bus access. I've tried disabling caches. I've counted the disassembly cycles. So far, absolutely nothing seems to bring that jitter down. To make this workable I need to have <20ns jitter in enabling the MCO.
The datapaths are quite complicated, but really I don't see any reason for 6+ cycles of jitter between all the AHB/APB bus and peripheral accesses in the bare minimum code. If there is any alternate way to start this damn clock nicely, I'd like to know too.