STM 32F4 - output pin "speed" setting - what does it actually do?

[peter-h]

This has come up here before so I did some careful measurements.

Firstly, it does not appear to be done by paralleling different size MOSFETs, because the data sheet has just one current capability spec:



It looks like a slew rate limit - maybe done by switching in of different capacitors into the signal driving the output MOSFETs:



The last-1 option seems the one to go for because ir produces less ringing (not evident in the traces below) and the last two show the same risetime, so limited by the 350MHz Lecroy 3034 scope + 1GHz probe. Some devices ask for a fast risetime. One Adesto SPI FLASH wants 3ns and a Lyontech SPI RAM wants 1.5ns!

[redkitedesign]

Firstly, it does not appear to be done by paralleling different size MOSFETs, because the data sheet has just one current capability spec:

The datasheet is about the DC rating, not about the transition. Since the speed setting seems to affect the transistion (and is called speed setting, not strength setting!) the final output drive strength can very well be the same for all speed settings.

Note that IC manufacturers can make any shape and geometry of FET they like. A single channel FET with multiple (overlapping) gates is very well possible, and can thus be modulated in channel size and therefor resistance. Note that capacitors are expensive in IC design, they take too much space.

[peter-h]

OK; they may have done that.

What surprises me is just how easy it is to get really clean waveforms with this CPU. Makes EMC compliance so much easier.

[thm_w]

Can dig into the references here if you really want: http://www.ics.ee.nctu.edu.tw/~mdker/International%20Conference%20Papers/2008%20ICECS_Design%20on%20mixed-voltage%20IO%20buffers%20with%20slew-rate%20control%20in%20low-voltage%20CMOS%20process.pdf

But yeah not having IO switching at FCPU is much nicer for many scenarios.

[T3sl4co1l]

More likely implemented by varying the number of transistors driving the final inverter.  So Miller plus drive resistance controls slope, while current capacity is independent.

Nice on the AVRs that have it, too (XMEGA, Dx).

Tim