Vias for BGA 0.8mm pitch

[Tobias89]

This is a 6-layer fanout, but the electrical clearance used is very conservative (0.15mm / 6 mils). You can optimize the layer count if you use 4 mils.

4 layers and normal vias doesn't seem possible to me. Either use a blind/burried vias or smaller clearance. If not both.

Ok, I understand.
Could we say that in a BGA up to the fourth row of balls we can get tracks with conventional vias and 4 layers, and beyond the fourth row it becomes complicated using only 4 layers?.

So far I have not needed to get so many tracks from a BGA, but I have a project with an STM32 and an SDRAM memory that may need many ports, the version I made was with LQFP from an STM32H747, but I would like to do it with a BGA.

For 0.8 mm pitch BGA, count that you can fan out the outer two rows with no vias (maybe even three rows, depending on the clearance rule). The next two rows can be fanned out via TH vias, yes.

But in this case you don't have any room left for the power and GND distribution, so it may not be too wise.
Especially if you have SDRAM - you need to carefully route this by taking care of the characteristic impedance of the traces and matched lengths.
I usually do this with 8 layers. 5 of them go to SDRAM traces:
 - GND,
- signal,
- GND,
- signal,
- GND.

I.e., you have two sets of asymmetric striplines. Trust me, you'll want this.

[asmi]

So far I have not needed to get so many tracks from a BGA, but I have a project with an STM32 and an SDRAM memory that may need many ports, the version I made was with LQFP from an STM32H747, but I would like to do it with a BGA.

STM32H747XI? I've done a nearly full breakout on just 4 layers.

[Tobias89]

So far I have not needed to get so many tracks from a BGA, but I have a project with an STM32 and an SDRAM memory that may need many ports, the version I made was with LQFP from an STM32H747, but I would like to do it with a BGA.

STM32H747XI? I've done a nearly full breakout on just 4 layers.

I'm not saying it's impossible. I just wanted to point out that in case of SDRAM routing, you're safer it will work if you have controlled impedance and lengths of the traces.

I'm curious, what interfaces have you routed in these 4 layers? What is the stackup? Have you done testing already?

[asmi]

I'm not saying it's impossible. I just wanted to point out that in case of SDRAM routing, you're safer it will work if you have controlled impedance and lengths of the traces.

That MCU runs SDRAM at like 90 MHz or so, for that kind of speed you've got to seriously screw things up for routing to become a problem. so I wouldn't worry too much about those issues, unless they are seriously out of whack.

I'm curious, what interfaces have you routed in these 4 layers? What is the stackup? Have you done testing already?

This was an SDR and it had a lot of stuff broken out - hence using such large package, notably it had QSPI running at 200 MHz connected to DDS, microSD card slot, some sensitive RF/analog stuff connected to ADCs, and a lot of GPIO for various control signals of RF part of the board. That board was implemented years ago (pre-COVID) and as far as I know all PCBs I've built are up and running fine.

[bson]

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For 0.8 mm pitch BGA, count that you can fan out the outer two rows with no vias (maybe even three rows, depending on the clearance rule). The next two rows can be fanned out via TH vias, yes.

But in this case you don't have any room left for the power and GND distribution, so it may not be too wise.

This really depends on the ballout.  Sometimes BGAs have supplies and oscillators in the outer two rows, in which case it's easy to decouple them closely on the top side and place a "frame" shape power plane around the outer perimeter on an inner layer.  The outside TH vias don't really make for much of a problem.

At other times, they're in the center, so don't need to be escaped at all and can just be connected with in-pad TH vias to a plane below.  They only make an obstacle for cross-package traces.

Note that the difficulty of escaping is not due to the number of pads per se, but the % of pads used.  If you go to a bigger package with more balls but don't use any of them you lower this percentage, creating openings that will make escaping it easier.

Here's two examples, one with power and XO along the outside, one combining this with power at the center.  Power in the center is IMO easiest to decouple on the opposite side.



Edit: I don't know why, but this idiotic forum software will only inline one of the images no matter how I try to tell it to inline both