STM32 DMA Transmission Paralleling

[syntax333]

Hi, I am trying to understand how the Bus Matrix work and how can I use the DMA most efficient way possible in STM32G431KB microcontroller.

In AN2548 Application Note Section 5.2, it says that " For example when using STM32L486, a DMA1 transfer from SRAM1 to AES can access the bus matrix simultaneously with DMA2 transfer from Flash memory to any APB communication interface. No conflict and arbitration occurs."

So does this mean that I can transfer the data I want in parallel, as long as I don't use the same bus?

For example:

In the Datasheet memory diagram it shows the ADCs connected to AHB2 Bus and USART1 is connected AHB1 Bus.

In the Reference Manual Bus matrix diagram it shows that DMA1 is connected to SRAM1 and AHB1 and DMA2 is connected to SRAM2 and AHB2.

So can I use the DMA2 to store ADC values to SRAM2 while transferring data from SRAM1 to USART1 using DMA1 simultaneously in parallel fashion?
Is this the most efficient way to do this kind of stuff?

Also does this mean that when I try to send data from SPI2 while receiving data from USART 1 (Same AHB1 bus), the data will be transferred in serial fashion from/to memory?

[uer166]

Also does this mean that when I try to send data from SPI2 while receiving data from USART 1 (Same AHB1 bus), the data will be transferred in serial fashion from/to memory?

Someone correct me if I'm wrong..

There is a round-robin scheduler that schedules transfers with all bus masters being equal priority. In that example, if two bus masters (say DMA1 and DMA2) want to transfer through AHB1, they just alternate: DMA1,DMA2,DMA1,DMA2.... etc. If CPU was also using AHB1, then it would be DMA1,DMA2,CPU,DMA1.. etc. This means it won't be serial (i.e. DMA1 transfers a big chunk, then DMA2 transfers a big chunk), but interleaved instead. I think each atomic transfer is 32 bits of data?

[uer166]

In the Datasheet memory diagram it shows the ADCs connected to AHB2 Bus and USART1 is connected AHB1 Bus.

In the Reference Manual Bus matrix diagram it shows that DMA1 is connected to SRAM1 and AHB1 and DMA2 is connected to SRAM2 and AHB2.

So can I use the DMA2 to store ADC values to SRAM2 while transferring data from SRAM1 to USART1 using DMA1 simultaneously in parallel fashion?
Is this the most efficient way to do this kind of stuff?

I believe that is correct, it would be parallel transfers assuming no common bus is used. Does this matter at all though? USART doesn't generate a lot of data, so even if you share a bus with another master (CPU or another DMA), who cares?