STM32 interrupt priority

[NiHaoMike]

I have a STM32F103 that I'm using to sniff I2C traffic, it mostly works but misses an interrupt occasionally causing it to read the wrong data. I read that STM32 supports setting the interrupt priority but I can't find any references to how to do that in PlatformIO with the Maple core. (I have to use the Maple core as it's the only one that supports the USBComposite library.)

I have considered adding another microcontroller just for sniffing I2C but that seems excessive when the STM32 should be able to handle it on its own.

[DavidAlfa]

Try nvic_set_priority() (libopencm3) or NVIC_SetPriority() / __NVIC_SetPriority() (HAL).

IRQ list:
libopencm3
HAL

[pcprogrammer]

Or just write directly to the registers like below.

Code: [Select]

  //Set priority for USB interrupt to be lower then the other interrupts
  //This is an array of 8 bit registers, of which only the upper 4 bits are used for the priority allowing for 16 levels
  //By grouping this is separated to allow for having sub priorities within a single group.
  //The higher the number the lower the priority
  NVIC->IP[USB_LP_CAN1_RX0_IRQn] = 0xC0;  //(1100b) Group priority 3, sub priority 0

More on this can be found in the attached manual.

[ajb]

The NVIC is part of the ARM architecture, not specific to the STM32 family, so if you want the gritty details those are in the ARM documentation.  It's a bit heavier reading that requires a lot of flipping back and forth to interpret everything, but worth knowing where to find this stuff when you need an in-depth answer.  The other information linked above is probably adequate to get what you need done, though.

The NVIC itself is described in the Cortex-M3 Technical Reference Manual: https://developer.arm.com/documentation/ddi0337/h/nested-vectored-interrupt-controller?_ga=2.258143811.839925519.1629395464-2030874199.1629395464
And the way the architecture handles exceptions/interrupts is described in the ARMv7-M Architecture Reference Manual: https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/ARMv7-M-exception-model?lang=en

[NiHaoMike]

Got it working, for reference with the Maple core, use this for interrupt pins 5-9:
nvic_irq_set_priority(NVIC_EXTI_9_5, 0);

And it helps to redefine the interrupt handler to only check the pins you're actually using.

Code: [Select]

extern "C" void __irq_exti9_5(void) {
digitalWrite(PC13, 0);
register uint32 pr = EXTI_BASE->PR;
register uint32 handled_msk = 0;
if(pr & 0x100) {
scl_s();
handled_msk = 0x100;
}
if(pr & 0x200) {
sda_s();
handled_msk |= 0x200;
}
EXTI_BASE->PR = (handled_msk);
asm volatile("nop");
asm volatile("nop");
digitalWrite(PC13, 1);
}
The "digitalWrite" lines are only for verification using a logic analyzer, they can be commented out when no longer needed. Not sure how necessary the "nop" lines are, they were part of the original interrupt handler and I'm sure there's a good reason why they're there.

[DavidAlfa]

16 levels.
Read RM0008, page 197.

[pcprogrammer]

Better to look into this manual and read the section about NVIC.

Edit: Fixed the link to the manual.

[DavidAlfa]

This manual?

http://file///home/peter/Downloads/pm0056-stm32f10xxx20xxx21xxxl1xxxx-cortexm3-programming-manual-stmicroelectronics.pdf

[pcprogrammer]

This manual?

http://file///home/peter/Downloads/pm0056-stm32f10xxx20xxx21xxxl1xxxx-cortexm3-programming-manual-stmicroelectronics.pdf

Whoops 

Fixed it in the original post.