Shifty Register behaviour

[PerranOak]

I have a uC connected to a 74HC595 shift register.

One GPIO0 is connected to HC595 "SER" (serial input) and GPIO1 is connected to both SRCLK and RCLK, i.e. tied together.

This simple programme will only work (it just runs through 0-255 to show-up on the LEDs attached to the HC595 outputs) if I add-in the last "pulse" just before the delay (the delay just aids viewing):

Code: [Select]

    while(1)
    {
        for (int display = 0; display < 256; display++)
        {
            for (int count = 0; count <8; count++)
            {
                GPIObits.GP0 = (display >> count) & 1;
                GPIObits.GP1 = 1;
                GPIObits.GP1 = 0;
            }
            GPIObits.GP1 = 1;
            GPIObits.GP1 = 0;
            __delay_ms(1000);
        }
    }
Without this extra, the numbers are not shifted far enough by one place.

Is this because the RCLK requires the extra pulse to copy the shifted bits into the output "stage"?

Cheers.

[langwadt]

the output of the shift register will change slightly after SRCLK, so the when SRCLK and RCLK happens at the same time the output register will latch the data right before the shift

[Jope]

Quote from the datasheet (Philips), title page: "If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register."

[PerranOak]

So, before I added the extra pulse it was “waiting” for another clock pulse. Cheers.