STM32 VCAP pins, OK to run with via?

[NaDobraNich]

I have a VQFN STM32U5 part.

Reading over the AN for power:
https://www.st.com/resource/en/application_note/an5419-getting-started-with-stm32h723733-stm32h725735-and-stm32h730-value-line-hardware-development-stmicroelectronics.pdf

I haven't been able to find an answer to a placement question. I have two VCAP pins for the internal 1.2V internal LDO. 2.2uF each, 0603 sized, enough voltage rating that I won't care about DC bias losses.

I can route those well enough on top, but it sure would be easier if I could but them on the bottom of my board and connect with a via.

I'm torn because I've read this bad for bypass, but these are larger. But then again, almost every FPGA in the world does this.

Is a via ok here?

[thm_w]

Whats normal trace 3nH per cm or so? A via might be less inductance than the trace.
If you really care you can put multiple vias. But I doubt it matters here.

DC bias losses are not related to voltage rating but to package size and material.

https://community.infineon.com/t5/Knowledge-Base-Articles/DC-Bias-characteristic-of-Multilayer-Ceramic-Capacitor-MLCC/ta-p/250035

[SiliconWizard]

Yes and the STM32U5 is an ultra low power device, the current spikes on the internal rail are nowhere near that of even a small FPGA.

[hans]

I'm using the STM32U5 in a project, and have it perform LPBAM wakeups at 8.2kHz and CPU wakeups at 128Hz. The current spikes during wakeup are only 2-5mA or so.

Those 2.2uF are also bulk caps, so at a few MHz their inductance is already going to dominate. As long as the ESR is low enough, it will probably work totally fine.

In my own design I did saw some trouble when powering the project from a coin cell (ESR of 1-10Ohms). But that was only because I'm using an extremely sensitive JFET amplifier that is tuned for uV level (RF) signals. Adding 100uF or so on the main supply and some extra filters fixed that issue.

[aliarifat794]

Using vias to connect decoupling capacitors on the bottom layer can be acceptable in many cases, especially for larger capacitors and lower-frequency applications.

[NaDobraNich]

Thanks @thm_w. You're right. My mistake. TDK's site has this great calc to check the DC bias estimation, and you're right. It's the same for the 6.3V and 10V parts in 0603. https://product.tdk.com/en/search/capacitor/ceramic/mlcc/list#ref=characteristic&1shape%5B%5D=2+Terminal&lw%5B%5D=1.6mm+x+0.8mm+%5BEIA+0603%5D&1cap%5Bunit%5D=1.00E-06&1cap%5Bt%5D=2.2&1tc%5B3%5D%5B%5D=X7R&psts%5B%5D=0&1a_dcbias%5Bt%5D=3.3&1a_dcbias%5Bl%5D=1&1a_dcbiasc_f%5Bt%5D=.1&1a_dcbiasc_t%5Bt%5D=10&1a_dcbiasc_t%5Bl%5D=1.00E-06&1rv%5Bcomp%5D=%3D&1rv%5Bdc%5D%5B%5D=6.3&1rv%5Bdc%5D%5B%5D=10&_l=20&_p=1&_c=part_no-part_no&_d=0&_106=1&_107=1

So, OK, I get that these are bulk caps, and "this should be fine". But can I get an estimate of how much worse it would be?

It's a 250Mhz (max speed) micro, the GPIOs are obviously slower than that, but I am concerned about whole system EMI (BLE radio and background testing).

If it's 10% worse in very high frequency noise at the micro to put caps on the bottom, then I'd consider it. I can get a tiny bit closer than on the top side. But the thing about this is that every BGA chip out there goes with bottom caps, and no one seems to care. I've never seen someone say "Oh don't use a BGA chip, you won't get peak bypass performance".

I lack a gut feel on this.

[thm_w]

You are using what is recommended per the link, which says "2.2 μF ESR < 100 mΩ for VCAP1, 2.2 μF ESR < 100 mΩ for VCAP2".
Most likely generic ceramic caps will have much lower than 100mR ESR already. X7R is always a good choice for quality design, which you have already.

If you do really care, I'm not sure why you are still saying its worse without calculating the trace and via inductances and comparing them. BGA usually has better performance due to lower lead lengths to the die:
https://en.wikipedia.org/wiki/Lead_frame#/media/File:TQFP_Leadframe.jpg

There are more important things to focus on IMO.

[NaDobraNich]

You are using what is recommended per the link, which says "2.2 μF ESR < 100 mΩ for VCAP1, 2.2 μF ESR < 100 mΩ for VCAP2".
Most likely generic ceramic caps will have much lower than 100mR ESR already. X7R is always a good choice for quality design, which you have already.

If you do really care, I'm not sure why you are still saying its worse without calculating the trace and via inductances and comparing them. BGA usually has better performance due to lower lead lengths to the die:
https://en.wikipedia.org/wiki/Lead_frame#/media/File:TQFP_Leadframe.jpg

There are more important things to focus on IMO.

I'm figuring the same length, but one option has a via and the other doesn't. When I say same length, I'm assuming the 1.2-1.6mm of 8 layer board is accounted for there. So, given the same trace lengths the one without the via is surely better. I just can't get and understanding for where on the list of more important things this is.

[SiliconWizard]

Using vias to connect decoupling capacitors on the bottom layer can be acceptable in many cases, especially for larger capacitors and lower-frequency applications.

Yes, and as hans said, those are not exactly bypass capacitors anyway, although they do partially act as ones too, but they are basically the output capacitors for the internal LDO, so any problem here is very unlikely.

[NaDobraNich]

Using vias to connect decoupling capacitors on the bottom layer can be acceptable in many cases, especially for larger capacitors and lower-frequency applications.

Yes, and as hans said, those are not exactly bypass capacitors anyway, although they do partially act as ones too, but they are basically the output capacitors for the internal LDO, so any problem here is very unlikely.

Right right, ok, see even though I read the words, it didn't really sink in. I'm not doing bypassing with these anyhow, just bulk. So all I would need to consider is the increased inductance of the via and if that would cause my core to be starved on a peak, but probably unlikely.

I am using the highest core frequency of 160Mhz, and highest AHB and etc frequencies. I can't remember what works off the internal 1.2V domain. But right right, not important most likely. Got it.

[thm_w]

I'm figuring the same length, but one option has a via and the other doesn't. When I say same length, I'm assuming the 1.2-1.6mm of 8 layer board is accounted for there. So, given the same trace lengths the one without the via is surely better. I just can't get and understanding for where on the list of more important things this is.

Calculate it and it might give you a better perspective.

This is very low on the list of important EMI issues and probably the board design in general.

[NaDobraNich]

I'm figuring the same length, but one option has a via and the other doesn't. When I say same length, I'm assuming the 1.2-1.6mm of 8 layer board is accounted for there. So, given the same trace lengths the one without the via is surely better. I just can't get and understanding for where on the list of more important things this is.

Calculate it and it might give you a better perspective.

This is very low on the list of important EMI issues and probably the board design in general.

Is it not obvious I do not know how to do that?

OK, I'll try.... And I could be WAY WAY off here... using a calculator, a blog, and AI I figured that:

Without vias for a .2mm trace, 1oz copper, 1.6mm board, ground plane is .1mm away from both the bottom and top planes, 2mm trace length, that it's 35.94nH of inductance. Then adding a via is 1.6nH. So.... 4.5% difference?

Is that remotely correct and what I would be looking for in negative effects here?

[thm_w]

Something in that ballpark yeah, 20-30nH.
Oh I didn't actually ask if you were using the BGA or TQFP part, just assumed it was the BGA one.

https://www.lingsen.com.tw/webc/html/assembly/pChar/tqfp.pdf guess leadframe is not that much.

[SiliconWizard]

You can use Saturn PCB Toolkit which is handy. https://saturnpcb.com/saturn-pcb-toolkit/

[NaDobraNich]

Something in that ballpark yeah, 20-30nH.
Oh I didn't actually ask if you were using the BGA or TQFP part, just assumed it was the BGA one.

https://www.lingsen.com.tw/webc/html/assembly/pChar/tqfp.pdf guess leadframe is not that much.

QFN part.Yea, if it was BGA I wouldn't think twice, right? But this was a good exercise to try just to see how "expensive" vias are on some signals.

[NaDobraNich]

You can use Saturn PCB Toolkit which is handy. https://saturnpcb.com/saturn-pcb-toolkit/

No linux version and doesn't run under Wine (boo!). But thanks, I'll get it in mind and run it on a remote machine maybe.

[SiliconWizard]

Yes it runs under Wine, using it. As I remember, it does crash if Wine's DPI setting is set to anything other than 96, though. So, something to check. Otherwise, no issues with it.

[NaDobraNich]

Yes it runs under Wine, using it. As I remember, it does crash if Wine's DPI setting is set to anything other than 96, though. So, something to check. Otherwise, no issues with it.

You're right. I feel dumb.

The installer errored out when trying to launch it from there. But going to the directory and running under wine works. Thanks!

It has reasonably close numbers to what I figured. This will be useful.