STM32F0 USB interface

[Red_Micro]

Anyone with experience using the crystal less USB interface from STM32F072? I have no external crystal. I've seen some unstable communication, sometimes disconnecting and connecting back multiple times fix it. I will start debugging so any suggestion is welcome. I read this from the errata sheet, which could be checked.

ESOF interrupt timing desynchronized after resume signaling
Description
Upon signaling resume, the device is expected to allow full 3 ms of time to the host or hub for sending the initial SOF (start of frame) packet, without triggering SUSP interrupt. However, the device only allows two full milliseconds and unduly triggers SUSP interrupt if it receives the initial packet within the third millisecond.
Workaround
When the device initiates resume (remote wakeup), mask the SUSP interrupt by setting the SUSPM bit for 3 ms, then unmask it by clearing SUSPM.

[pigrew]

Run optimized code, sometimes debugging/unoptimized code causes latency to be too high for USB.

Verify mechanicals and schematic. Do you have too much series resistance on D+/D-? Is Vdd dropping out? Too much capacitance on the data lines? Bad solder joints?

A photo of your PCB (and perhaps schematic) could also help.

[lbthomsen]

I have not tried crystal less USB on the STM32F072 (does that even exist or do you mean STM32L072?), but I have done this using an STM32L432 and that works flawlessly.

//Lars...

[GromBeestje]

Did you enable Automatic Clock Trimming?

[teletypeguy]

I have not used internal oscillator for usb, though as grombeestje pointed out, clock trimming is likely important.  I am interested how that works out.

What kind of device does it enumerate as, and what kind of data rate?

I have used many 072 and 042 parts as usb hid devices, though with an 8meg xtal.  Never a glitch on the streaming data -- well, until the test house clamped a sleeve around the cable for hv pulse immunity testing -- it didn't like that 

Layout could affect it if you don't have a short-ish/straight-ish 90-ohm diff pair, smooth transitions to the series resistors...  A tvs should be a must, and a common-mode choke is a decent addition.  I had pll spurs to knock down and found that 47pF from each trace to ground fixed that without affecting data.

[PCB.Wiz]

Anyone with experience using the crystal less USB interface from STM32F072?.

I've not used that part, but they all have a largely common approach of a 1ms based DFLL.

You could try with a crystal, and confirm the problems go away - that confirms it is not any SW related issue.

You could output the divided OSC to a pin, and put a counter on that - a 1ms pin toggle is likely to match any DPLL update rate, as they use USB SOF as the locking clock.

You should see that lock, when USB is connected and the SW operates correctly.
The lock granularity will be limited by the LSB of the trim steps, but the frequency should jitter about a long term average of the PC clock.