stm32f042k6 boot with power switch only? (no reset)

[marikka]

I've been working on a small game based on the stm32f042k6. This is my first microcontroller design. I've attached the schematic as mp1.1.png
I've used figure 10 on page 33 of this datasheet as reference: https://www.st.com/content/ccc/resource/technical/document/user_manual/e3/0e/88/05/e8/74/43/a0/DM00231744.pdf/files/DM00231744.pdf/jcr:content/translations/en.DM00231744.pdf

Currently my circuit works, but I need to connect NRST to GND to start after I turn the power switch on.
Can you please help me understand, what exactly needs to happen for the MCU to boot when I turn on the power switch, without a hardware reset? I'm thinking of adding a reset button in my next iteration, but as this is a minimalist design, I'd really like to avoid that.

I am aware that I'm missing some things from the reference design. Can you help me understand the meaning of these:
1. A reset switch, with a 100nF capacitor in parallel.
2. A 100nF capacitor between GND and AVDD
3. A BEAD (Ferrite bead?) between AVDD and VDD

3.5.2 Power supply supervisors in this datasheet https://www.st.com/resource/en/datasheet/stm32f042c6.pdf says:
"The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD."
Is this my problem? How can I ensure that VDDA arrives first? Is the bead or the capacitor essential for this to work?

Thank you in advance for helping me understand this

[Siwastaja]

STM32 chips (at least some) require a 100nF (or thereabouts) capacitor between NRST and GND. This information is buried in very strange places within thousands of pages of documentation - not in the relevant datasheet section - it took me over five years to find it for the first time, before that my designs happened to work by luck without the capacitor.

You don't usually want a physical reset switch, IMHO.

[newbrain]

1. A reset switch, with a 100nF capacitor in parallel.

Siwastaja covered this, and I cannot but agree with them.

3. A BEAD (Ferrite bead?) between AVDD and VDD

Though good practice, I admit never using it (unless I need the ADC).
I never had reset problems.
Decoupling is important, but I see you have a couple of 100 nF caps.

Another thing I notice is the direct connection of user buttons to the GPIO pin: I can imagine you are using the internal pull-ups and a debouncing is completely carried out in SW.
Depending how it's done, it might get flaky with buttons aging; many reference boards include a bit of HW debounce too:

It has a stronger pull-up, and and an RC network to avoid 'stressing' the button with the capacitor discharge.

This information is buried in very strange places within thousands of pages of documentation - not in the relevant datasheet section

Eh, recommended in Picture 25 in the NRST Pin Characteristics, but easily overlooked.
What is even worse is that the AN4080 "Getting started with STM32F0x1/x2/x8  hardware development" only shows it in the reference design, and does not mention it in the System Reset chapter.

You don't usually want a physical reset switch, IMHO.

Useful for development, maybe.

Edited: The (fire)fox ate my homework...

[Siwastaja]

Eh, recommended in Picture 25 in the NRST Pin Characteristics, but easily overlooked.

Fig. 22 in h743 datasheet I'm looking at, shows an optional combination of reset switch paralleled with the 100nF; their combination is circled and labeled as "External reset circuit", and the footnote says: "The reset network protects the device against parasitic resets." For any seasoned designer, this implies that the capacitor is recommended when the physical switch is used, for "protection" (presumably debouncing and ESD/EMI filtration). Naturally, without the "external reset circuit" connected, such "recommended protection" is not needed.

Of course, this is not the issue here, at all. The issue isn't spurious resets, EMI, ESD or whatever. Without the 100nF cap, the MCU may fail to boot completely. The capacitor is needed as a functional part of their internal reset circuitry to work properly. I'm guessing they have an edge detector which relies on delayed rise of the reset signal, or something similar going on.

They just fail to document that completely in the datasheet. The only place where they specify that the capacitor is actually needed, is in the reference manual (where it doesn't belong), for example page 310 on the H743 reference manual I'm looking at:
"It is not recommended to let the NRST pin unconnected. When it is not used, connect this pin to ground via a 10 to 100 nF capacitor (C R in Figure 39)."

And this is very hard to find from 3247 pages of documentation which is supposed to describe the internal logic, peripherals and registers, and doesn't talk anything else regarding schematic capture or PCB design, and constantly redirects the reader to the datasheet whenever talking about electrical properties and external components.

[marikka]

Kiitos, anteeksi, tack och förlot Siwastaja and newbrain! Your help is very much appreciated.

After leaving this problem be for a while, I suddenly realized that this is a software problem.
I'm using an I2C OLED display, and somehow it must not be ready when the MCU is. If I add a short delay in the beginning, it works fine. NRST and GND are completely disconnected, no caps or switches.

I was so focused on trying to figure out the unfamiliar (the hardware), that I got completely blind to an obvious source of error.

[OwO]

That is strange, both the stm32f1 and stm32f0 datasheets have this text:

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V POR/PDR , without the need for an external reset circuit.

The capacitor approach is really dumb because it relies on a minimum Vcc slew rate to work at all (if power supply comes up slowly NRST will always be at Vcc). If these chips really don't have a power supervisor that means one is needed externally, which really sucks.

[Siwastaja]

That is strange, both the stm32f1 and stm32f0 datasheets have this text:

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V POR/PDR , without the need for an external reset circuit.

The capacitor approach is really dumb because it relies on a minimum Vcc slew rate to work at all (if power supply comes up slowly NRST will always be at Vcc). If these chips really don't have a power supervisor that means one is needed externally, which really sucks.

They are clearly not giving us enough information to really know what's going on. Recently I had a H743 which won't boot up unless I touched the NRST pin with an oscilloscope probe - then text searching for "NRST" from all 4000 pages of documentation found me the part I quoted above, and adding the cap solved the problem. And while it's clearly included in (at least some) devboards, I'm not the only one who has successfully made several designs without the capacitor whatsoever.

MCU manufacturers seem to have problems creating proper reset circuits. I remember early AVRs did have problems as well, and needed external reset circuitry to work really reliably. The idea is that they integrate everything and make it work without external components (a desirable goal), but then have some bug that pops up rarely, in some edge cases, causing endless pain.