Also don't pay much attention to what the plugin in the debugger shows you - RM is the definitive source, so it it says you have two "M" bits then you have two of them, even if debugger tries to say otherwise.
Actually I think the STM32F302xSVD file may be the definitive source as there are errors in the STM32F Reference Manuals here and there. This isn't surprising when one considers the *massive* numbers of peripherals, registers and bit-fields in their enormous range of MCU's.
The STM32F302x.svd shows no bit 28 in USARTX_CR1. The words "Word length" (CR1_M) only occur for bit 12 in USARTX_CR1.
This is a Forth Word List generated from STM32F302x.svd, but it shows the full bitfield names and descriptions.
\ USART2_CR1 (read-write)
: USART2_CR1_EOBIE %1 27 lshift USART2_CR1 bis! ; \ USART2_CR1_EOBIE End of Block interrupt enable
: USART2_CR1_RTOIE %1 26 lshift USART2_CR1 bis! ; \ USART2_CR1_RTOIE Receiver timeout interrupt enable
: USART2_CR1_DEAT ( %XXXXX -- ) 21 lshift USART2_CR1 bis! ; \ USART2_CR1_DEAT Driver Enable assertion time
: USART2_CR1_DEDT ( %XXXXX -- ) 16 lshift USART2_CR1 bis! ; \ USART2_CR1_DEDT Driver Enable deassertion time
: USART2_CR1_OVER8 %1 15 lshift USART2_CR1 bis! ; \ USART2_CR1_OVER8 Oversampling mode
: USART2_CR1_CMIE %1 14 lshift USART2_CR1 bis! ; \ USART2_CR1_CMIE Character match interrupt enable
: USART2_CR1_MME %1 13 lshift USART2_CR1 bis! ; \ USART2_CR1_MME Mute mode enable
: USART2_CR1_M %1 12 lshift USART2_CR1 bis! ; \ USART2_CR1_M Word length
: USART2_CR1_WAKE %1 11 lshift USART2_CR1 bis! ; \ USART2_CR1_WAKE Receiver wakeup method
: USART2_CR1_PCE %1 10 lshift USART2_CR1 bis! ; \ USART2_CR1_PCE Parity control enable
: USART2_CR1_PS %1 9 lshift USART2_CR1 bis! ; \ USART2_CR1_PS Parity selection
: USART2_CR1_PEIE %1 8 lshift USART2_CR1 bis! ; \ USART2_CR1_PEIE PE interrupt enable
: USART2_CR1_TXEIE %1 7 lshift USART2_CR1 bis! ; \ USART2_CR1_TXEIE interrupt enable
: USART2_CR1_TCIE %1 6 lshift USART2_CR1 bis! ; \ USART2_CR1_TCIE Transmission complete interrupt enable
: USART2_CR1_RXNEIE %1 5 lshift USART2_CR1 bis! ; \ USART2_CR1_RXNEIE RXNE interrupt enable
: USART2_CR1_IDLEIE %1 4 lshift USART2_CR1 bis! ; \ USART2_CR1_IDLEIE IDLE interrupt enable
: USART2_CR1_TE %1 3 lshift USART2_CR1 bis! ; \ USART2_CR1_TE Transmitter enable
: USART2_CR1_RE %1 2 lshift USART2_CR1 bis! ; \ USART2_CR1_RE Receiver enable
: USART2_CR1_UESM %1 1 lshift USART2_CR1 bis! ; \ USART2_CR1_UESM USART enable in Stop mode
: USART2_CR1_UE %1 0 lshift USART2_CR1 bis! ; \ USART2_CR1_UE USART enable