STM32F4 + External SRAM

[spaghetti]

I have a couple of external SRAM chips I need to test. Would it be possible to just hook the pins of the SRAM directly to the STM32 GPIO?
The SRAM datasheet says read and write cycle times should be a minimum of around 20 ns. However, assuming I run my STM32 at 25MHz, my clock cycle is already 40ns, which seems to suffice the requirements.In this case, would it be fine to control the CS#, OE#, and WE# pins to read and write data to the SRAM or should I really hook it up to an FPGA?
P.S. I do not want to use the FMC utility ST provides. Just barebones code to test I can read and write data to the SRAM.

[iMo]

Yes, provided your sram is 3.3V you can do it, indeed.
PS: I ran a 512kB sram (10ns, 3.3V) on the stm32F103/407 FSMC bus as well, you may even run the binary out of the external sram (or to use the ext. sram as the heap).

PS: when bitbanging your sram off the C code the access times will be much longer than 40ns clock, so no worries with the 20ns sram..

[spaghetti]

Yes, provided your sram is 3.3V you can do it, indeed.
PS: I ran a 512kB sram (10ns, 3.3V) on the stm32F103/407 FSMC bus as well, you may even run the binary out of the external sram (or to use the ext. sram as the heap).

PS: when bitbanging your sram off the C code the access times will be much longer than 40ns clock, so no worries with the 20ns sram..

Thanks for the quick reply. I do plan to bitbang the data to individual addresses and then read it for verification. But I also need UART/I2C for other peripherals, and to be honest understanding the Xilinx AXI protocol feels climbing the Everest. So thought might as well use a system I am familiar with to save time. Thanks again!

[bson]

An 8-bit SRAM should plug directly into the FSMC bus.  For a 16-bit SRAM you'll need a larger package (read: BGA) to get both 16-bit data and the low 16 bits of the address bus.

[SiliconWizard]

Of course you can. SRAM can be accessed as slowly as you want, so you can definitely bit-bang address and control pins as long as you use an appropriate sequence (and of course as long as you have enough GPIOs available.)

[spaghetti]

An 8-bit SRAM should plug directly into the FSMC bus.  For a 16-bit SRAM you'll need a larger package (read: BGA) to get both 16-bit data and the low 16 bits of the address bus.

Yes, I looked into that first, to use FSMC. But I have 2 SRAMs (64k x 8b and 128k x 8b), and the entire setup for that seems really time consuming, especially since it is the first time I would be using it. Instead I figured I can just hook up the pins to GPIO and manually write a firmware quickly. Just wanted to confirm if it was really possible before going ahead with the design.

[wek]

> the entire setup for that seems really time consuming

- enable GPIOs clock in RCC
- set FSMC pins to AF in GPIOx_MODER, appropriate AF number in GPIOx_AFR[], probably you want also set nondefault speed in GPIOx_OSPEEDR
- enable FSMC clock in RCC
- set two registers in FSMC for selected bank - one determines timing, you can leave it at default at the low system clock, the other's fields are well described for the particular case of SRAM in the first of the series of tables in RM for the various modes of the static/non NAND part in FSMC.

I'd recommend you to wire the memory up to the FSMC pins, even if you are going to use bitbanging initially.

JW