Electronics > Microcontrollers

STM32F417 - any reason why a min PCLK2 speed is required for ethernet to work?

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peter-h:
With a 168MHz core, I am finding it runs with DIV8 i.e. 21MHz, or anything faster, but fails with DIV16.

There isn't anything in the ST ethernet code AFAIK which relates to PCLK2. Ethernet uses its own 48MHz source.

There are 2 timers - systick and tim6, both running at 1kHz, neither related to PCLK1.

Could it be there is some data sampling issue which requires PCLK2 to run at x times something?

Needless to say debugging this will be complicated.

I don't need 10.5MHz PCLK2; it is just handy for low baud rates:
https://www.eevblog.com/forum/microcontrollers/32f417-any-way-to-get-baud-rates-below-1200/

EDIT: it turns out somebody has been here before, and as usual without any resolution:
https://community.st.com/s/question/0D50X00009Xkgdi/ethernet-mac-stops-transmitting-when-apb2-divided-by-16-stm32f407

It appears that slowing down PCLK1 is ok, but that screws up SPI2,SPI3 and other stuff.

Problem is one can't use DIV8 (21MHz) because one doesn't know the margin, so the slowest sensible PCLK2 is DIV4 (42MHz) if you are using ethernet.

wek:
Today I tried to set APB2 clock to AHB/16 on an 'F427 (which is almost identical to the 'F405/407/415/417) and ETH worked as usually.

I don't Cube.

Debug as usually - start with checking you have properly set clocks in RCC, check presence of the 25MHz/50MHz clock (do you use MII or RMII? What's your hardware? How do you generate the ETH clock?). Check, if SMII/MDIO works, observe waveforms on pins, check that PHY responds properly. Read out and check/compare ETH registers content.

> EDIT: it turns out somebody has been here before, and as usual without any resolution:

As usual, that somebody did not care to pursue the problem.

JW

peter-h:
This is the clock config



There was another report somewhere of this issue, and it said that the width of the pulses on the ethernet cable shrinks when you do DIV16 on PCLK2.

This is not related to Cube IDE; well not in any obvious way.

The hardware is based on their dev board i.e. LAN8742 fed with a 50MHz clock from PA1. 32F417 xtal is 25MHz. The frequencies of PCLK1, PCLK2 have been checked in several ways, including viewing SPI2/3 clocks with a scope.

Of course, the cause could be some third factor.

Frankly, most people are not able to pursue this sort of thing, at the physical layer, because of the expertise required, not to mention the equipment, and they will already have spent so much time debugging the ST drivers.

wek:

--- Quote ---There was another report somewhere of this issue, and it said that the width of the pulses on the ethernet cable shrinks when you do DIV16 on PCLK2.
--- End quote ---

Can you please give a link to this claim?


--- Quote ---This is not related to Cube IDE; well not in any obvious way.
--- End quote ---

No, the IDE is just that, an IDE (more precisely, Eclipse).  By Cube I mean the whole "ecosystem", of which the central part is the "library", in this case, CubeF4.


--- Quote ---The hardware is based on their dev board
--- End quote ---

Who is "them", ST? Which dev board in particular?

PA1 is input in this case, ETH_RMII_REF_CLK. So the 50MHz clock is generated by PHY; what is the clock source to that PHY, then?

You can also try to run your code on said dev board, to have a "known good" reference point.


--- Quote ---Frankly, most people are not able to pursue this sort of thing
--- End quote ---

That's why there are more ready-made solutions like the Wiznet chips, or boards like RPi, around.

JW

peter-h:
The 50MHz comes from the LAN8742:



Same as the dev board, IIRC - the STM32F407G-DISC1. The ethernet stuff is on STM32F4DIS-EXT.





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