Author Topic: STM32F7 problem with MCO2 output derived from PLLI2SR  (Read 968 times)

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Offline prasimix

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STM32F7 problem with MCO2 output derived from PLLI2SR
« on: September 25, 2018, 04:10:04 pm »
I found that MCO2 output when derived from PLLI2SR doesn't work on STM32F769IGT6. I've selected as HSE input 10 MHz xtal that is running fine and using the following clock configuration (.ioc can be found in attachment):



Why is that? I didn't find so far that PLLI2SR cannot be used as a source, neither CubeMX report any error or warning. I'd like to use 25 MHz as clock for Ethernet PHY instead of deploying additional xtal/xco. Thanks in advance for your comments.


Offline MT

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Re: STM32F7 problem with MCO2 output derived from PLLI2SR
« Reply #1 on: September 25, 2018, 08:13:12 pm »
Have you tried "direct register writes" to setup GPIO and muxes to enable MCO as to absolutely sure the setup is valid.
(checking with you tools that register bits are really set or not).
« Last Edit: September 25, 2018, 08:15:01 pm by MT »
 

Offline prasimix

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Re: STM32F7 problem with MCO2 output derived from PLLI2SR
« Reply #2 on: September 26, 2018, 02:37:47 pm »
I've checked code which CubeMX generated and it seems that is in line with description in STM32F7 datasheet (RM0410 Reference manual, en.DM00224583). But, something else catches my attention and that is message what appears when hovering over disabled PLLI2SR combo box (see picture below), which says that SAI or DFSDM have to be enabled. Maybe it's simply not possible to use PLLI2SR as I presumed.





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