I do some performance evaluation of the adc, board is nucleo-G474re from ST. My intention mostly for high freq. application, when adc is running in undersampling mode with 20 MHz at the inputs (max so far I could get with Rigol).
Changing adc clock from 40 MHz, up to 56 MHz I 've made one mistake, configuring async_1 driven by PLL_P I missed to change P divider to 6, and default was 2. I couldn't believe, but SA application shows correct shift in freq. x3, sampling rate jumps to 11.2 msps w/o any noticeable difference in SNR !!!.
To be safe, I verified current consumption by nucleo+TFT+driver module and seen 3 mA only increase, from 217 mA to 220 mA
Here is some pictures, two taken with 42 MHz clock /15 = 2.8 msps and two with 168 / 15 = 11.2 msps